NXP Semiconductors freescale KV4 Series, Reference Manual

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PWMA_SMnCTRL field descriptions
Field Description
15–12
LDFQ
These buffered read/write bits select the PWM load frequency. Reset clears LDFQ, selecting loading
every PWM opportunity. A PWM opportunity is determined by HALF and FULL.
NOTE: LDFQ takes effect when the current load cycle is complete, regardless of the state of
MCTRL[LDOK]. Reading LDFQ reads the buffered values and not necessarily the values
currently in effect.
0000 Every PWM opportunity
0001 Every 2 PWM opportunities
0010 Every 3 PWM opportunities
0011 Every 4 PWM opportunities
0100 Every 5 PWM opportunities
0101 Every 6 PWM opportunities
0110 Every 7 PWM opportunities
0111 Every 8 PWM opportunities
1000 Every 9 PWM opportunities
1001 Every 10 PWM opportunities
1010 Every 11 PWM opportunities
1011 Every 12 PWM opportunities
1100 Every 13 PWM opportunities
1101 Every 14 PWM opportunities
1110 Every 15 PWM opportunities
1111 Every 16 PWM opportunities
11
HALF
Half Cycle Reload
This read/write bit enables half-cycle reloads. A half cycle is defined by when the submodule counter
matches the VAL0 register and does not have to be half way through the PWM cycle.
0 Half-cycle reloads disabled.
1 Half-cycle reloads enabled.
10
FULL
Full Cycle Reload
This read/write bit enables full-cycle reloads. A full cycle is defined by when the submodule counter
matches the VAL1 register. Either CTRL[HALF] or CTRL[FULL] must be set in order to move the buffered
data into the registers used by the PWM generators or CTRL[LDMOD] must be set. If both CTRL[HALF]
and CTRL[FULL] are set, then reloads can occur twice per cycle.
0 Full-cycle reloads disabled.
1 Full-cycle reloads enabled.
9–8
DT
Deadtime
These read only bits reflect the sampled values of the PWM_X input at the end of each deadtime.
Sampling occurs at the end of deadtime 0 for DT[0] and the end of deadtime 1 for DT[1]. Reset clears
these bits.
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–4
PRSC
Prescaler
These buffered read/write bits select the divide ratio of the PWM clock frequency selected by
CTRL2[CLK_SEL].
Table continues on the next page...
Memory Map and Registers
KV4x Reference Manual, Rev. 2, 02/2015
784
Preliminary
Freescale Semiconductor, Inc.