NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 1095 / 1359

CANx_CTRL1 field descriptions (continued)
Field Description
In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field,
generating an internal acknowledge bit to ensure proper reception of its own message. Both transmit and
receive interrupts are generated. This bit can be written only in Freeze mode because it is blocked by
hardware in other modes.
NOTE: In this mode, the CAN_MCR[SRXDIS] cannot be asserted because this will impede the self
reception of a transmitted message.
0 Loop Back disabled.
1 Loop Back enabled.
11
TWRNMSK
Tx Warning Interrupt Mask
This bit provides a mask for the Tx Warning Interrupt associated with the TWRNINT flag in the Error and
Status Register 1 (ESR1). This bit is read as zero when CAN_MCR[WRNEN] bit is negated. This bit can
be written only if CAN_MCR[WRNEN] bit is asserted.
0 Tx Warning Interrupt disabled.
1 Tx Warning Interrupt enabled.
10
RWRNMSK
Rx Warning Interrupt Mask
This bit provides a mask for the Rx Warning Interrupt associated with the RWRNINT flag in the Error and
Status Register 1 (ESR1). This bit is read as zero when CAN_MCR[WRNEN] bit is negated. This bit can
be written only if CAN_MCR[WRNEN] bit is asserted.
0 Rx Warning Interrupt disabled.
1 Rx Warning Interrupt enabled.
9
Reserved
This field is reserved.
8
Reserved
This field is reserved.
7
SMP
CAN Bit Sampling
This bit defines the sampling mode of CAN bits at the Rx input. It can be written in Freeze mode only
because it is blocked by hardware in other modes.
NOTE: For proper operation, to assert SMP it is necessary to guarantee a minimum value of 2 TQs in
CAN_CTRL1[PSEG1] (or CAN_CBT[EPSEG1]).
0 Just one sample is used to determine the bit value.
1 Three samples are used to determine the value of the received bit: the regular one (sample point) and
2 preceding samples; a majority rule is used.
6
BOFFREC
Bus Off Recovery
This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated, automatic recovering from
Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted, automatic recovering
from Bus Off is disabled and the module remains in Bus Off state until the bit is negated by the user. If the
negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus, then Bus Off
recovery happens as if the BOFFREC bit had never been asserted. If the negation occurs after 128
sequences of 11 recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for 11
recessive bits before joining the bus. After negation, the BOFFREC bit can be re-asserted again during
Bus Off, but it will be effective only the next time the module enters Bus Off. If BOFFREC was negated
when the module entered Bus Off, asserting it during Bus Off will not be effective for the current Bus Off
recovery.
Table continues on the next page...
Chapter 43 Flex Controller Area Network (FlexCAN)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
1095