NXP Semiconductors freescale KV4 Series, Reference Manual

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In Master mode, the CTAR registers define combinations of transfer attributes such as
frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. In
slave mode, a subset of the bitfields in CTAR0 are used to set the slave transfer attributes.
When the module is configured as an SPI master, the CTAS field in the command portion
of the TX FIFO entry selects which of the CTAR registers is used. When the module is
configured as an SPI bus slave, it uses the CTAR0 register.
Address: 4002_C000h base + Ch (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DBR FMSZ
CPOL CPHA
LSBFE
PCSSCK PASC PDT PBR
W
Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CSSCK ASC DT BR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPI_CTARn field descriptions
Field Description
31
DBR
Double Baud Rate
Doubles the effective baud rate of the Serial Communications Clock (SCK). This field is used only in
master mode. It effectively halves the Baud Rate division ratio, supporting faster frequencies, and odd
division ratios for the Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
Serial Communications Clock (SCK) depends on the value in the Baud Rate Prescaler and the Clock
Phase bit as listed in the following table. See the BR field description for details on how to compute the
baud rate.
Table 44-15. SPI SCK Duty Cycle
DBR CPHA PBR SCK Duty Cycle
0 any any 50/50
1 0 00 50/50
1 0 01 33/66
1 0 10 40/60
1 0 11 43/57
1 1 00 50/50
1 1 01 66/33
1 1 10 60/40
1 1 11 57/43
Table continues on the next page...
Memory Map/Register Definition
KV4x Reference Manual, Rev. 2, 02/2015
1184
Preliminary
Freescale Semiconductor, Inc.