NXP Semiconductors freescale KV4 Series, Reference Manual

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• If during system start-up, only one node is operating, then its TXERRCNT increases
in each message it is trying to transmit, as a result of acknowledge errors (indicated
by the ACKERR bit in the Error and Status Register). After the transition to "Error
Passive" state, the TXERRCNT does not increment anymore by acknowledge errors.
Therefore the device never goes to the "Bus Off" state.
• If the RXERRCNT increases to a value greater than 127, it is not incremented
further, even if more errors are detected while being a receiver. At the next
successful message reception, the counter is set to a value between 119 and 127 to
resume to "Error Active" state.
Address: Base a 1Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved Reserved RXERRCNT TXERRCNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_ECR field descriptions
Field Description
31–24
Reserved
This field is reserved.
23–16
Reserved
This field is reserved.
15–8
RXERRCNT
Receive Error Counter
Receive Error Counter for all errors detected in received messages. The RXERRCNT counter is read-only
except in Freeze mode, where it can be written by the CPU.
TXERRCNT Transmit Error Counter
Transmit Error Counter for all errors detected in transmitted messages. The TXERRCNT counter is read-
only except in Freeze mode, where it can be written by the CPU.
43.4.9 Error and Status 1 register (CANx_ESR1)
This register reports various error conditions detected in the reception and transmission of
a CAN frame, some general status of the device and it is the source of some interrupts to
the CPU.
The reported error conditions are BIT1ERR, BIT0ERR, ACKKERR, CRCERR,
FRMERR and STFERR.
An error detected in a single CAN frame may be reported by one or more error flags.
Also, error reporting is cummulative in case more error events happen in the next frames
while the CPU does not attempt to read this register.
TXWRN, RXWRN, IDLE, TX, FLTCONF, RX and SYNCH are status bits.
Chapter 43 Flex Controller Area Network (FlexCAN)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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