NXP Semiconductors freescale KV4 Series, Reference Manual

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PDBx_DACINTn field descriptions (continued)
Field Description
These bits specify the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update
when the DAC interval counter is equal to the DACINT. Reading these bits returns the value of internal
register that is effective for the current PDB cycle.
38.4.13 Pulse-Out n Enable register (PDBx_POEN)
Address: Base a 190h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
POEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POEN field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
POEN PDB Pulse-Out Enable
Enables the pulse output. Only lower Y bits are implemented in this MCU.
0 PDB Pulse-Out disabled
1 PDB Pulse-Out enabled
38.4.14 Pulse-Out n Delay register (PDBx_POnDLY)
Address: Base a 194h (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLY1 DLY2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POnDLY field descriptions
Field Description
31–16
DLY1
PDB Pulse-Out Delay 1
These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when the PDB counter is
equal to the DLY1. Reading these bits returns the value of internal register that is effective for the current
PDB cycle.
DLY2 PDB Pulse-Out Delay 2
These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is
equal to the DLY2. Reading these bits returns the value of internal register that is effective for the current
PDB cycle.
Chapter 38 Programmable Delay Block (PDB)
KV4x Reference Manual, Rev. 2, 02/2015
Freescale Semiconductor, Inc.
Preliminary
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