NXP Semiconductors freescale KV4 Series, Reference Manual

Page: 140 / 1359

Table 11-1. Ports summary (continued)
Feature Port A Port B Port C Port D Port E
Slew rate enable
control
Yes Yes Yes Yes Yes
Slew rate enable at
reset
Disabled Disabled Disabled Disabled Disabled
Passive filter
enable control
PTA4=Yes;
Others=No No No No No
Passive filter
enable at reset
Disabled Disabled Disabled Disabled Disabled
Open drain enable
control
1
Yes, pseudo open-
drain capability Yes, pseudo open-
drain capability Yes. PTC6, PTC7
are true open drain,
others are pseudo
open-drain
capability Yes, pseudo open-
drain capability Yes, pseudo open-
drain capability
Open drain enable
at reset
Disabled Disabled Disabled Disabled Disabled
Drive strength
enable control No PTB0/PTB1 only PTC3/PTC4 only PTD4/PTD5/PTD6/
PTD7 only No
Drive strength
enable at reset
Disabled Disabled Disabled Disabled Disabled
Pin mux control Yes Yes Yes Yes Yes
Pin mux at reset PTA0/PTA1/PTA2/
PTA3/PTA4=ALT7;
Others=ALT0 ALT0 ALT0 ALT0 ALT0
Lock bit Yes Yes Yes Yes Yes
Interrupt and DMA
request
Yes Yes Yes Yes Yes
Digital glitch filter No No No Yes No
1. • Pseudo open-drain is implemented to disable PMOS by setting PORTx_PCRn[ODE] so that external power supply
can’t be higher than the PAD power supply.
• For true open-drain pad, there is only one NMOS to output ‘0’ and can’t be controlled by PORTx_PCRn[ODE] bit.
11.3 Clock gating
The clock to the port control module can be gated on and off using the SCGC5[PORTx]
bits in the SIM module. These bits are cleared after any reset, which disables the clock to
the corresponding module to conserve power. Prior to initializing the corresponding
module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off
the clock, make sure to disable the module. For more details, refer to the clock
distribution chapter.
Clock gating
KV4x Reference Manual, Rev. 2, 02/2015
140
Preliminary
Freescale Semiconductor, Inc.