MPC563XM Reference Manual, Rev. 1
Freescale Semiconductor
205
Preliminary—Subject to Change Without Notice
Several prefetch control algorithms are available for controlling line read buffer fills. Prefetch triggering
may be restricted to instruction accesses only, data accesses only, or may be unrestricted. Prefetch
triggering may also be controlled on a per-master basis.
Buffers may also be selectively enabled or disabled for allocation by instruction and data prefetch.
Access protections may be applied on a per-master basis for both reads and writes to support security and
privilege mechanisms.
10.2.6.1
Basic Interface Protocol
The PFLASH_C90FL interfaces to the flash array by driving addresses and read or write enable signals to
the Flash Memory Interface unit. The access time of the Flash is determined by the settings of the
wait-state control bits in the PFCR1 register, as well as the pipelining of addresses.
The PFLASH_C90FL also has the capability of extending the normal system bus access timing by
inserting additional primary (initial access) wait states for reads, burst reads, writes, and burst writes. This
capability is provided to allow emulation of other memories which have different access time
characteristics.
10.2.6.2
Access Protections
The PFlash Memory Controller provides hardware configurable access protections for both read and write
cycles from masters. It allows restriction of read and write requests on a per-master basis. The
PFLASH_C90FL also supports software configurable access protections. Detection of a protection
violation results in an error response from the PFlash Memory Controller to the system bus.
10.2.6.3
Read Cycles - Buffer miss
Read data is normally stored in the least-recently updated line read buffer in parallel with the requested
data being forwarded to the system bus. If the flash access was directly the result of a system bus
transaction, the line buffer is marked as most-recently-used as it is being loaded. If the flash access was
the result of a speculative prefetch to the next sequential line, it is first loaded into the least-recently-used
buffer. The status of this buffer is not changed to most-recently-used until a subsequent buffer hit occurs.
10.2.6.4
Read Cycles - Buffer hit
Single clock read responses to the system bus are possible with the PFlash Memory Controller when the
requested read access is buffered.
10.2.6.5
Access Pipelining
Accesses to the Flash array can be pipelined by driving a subsequent access address and control signals
while waiting for the current access to complete. Pipelined access requests are always run to completion
and are not aborted by the PFlash Memory Controller. Request pipelining allows for improved
performance by reducing the access latency seen by the system bus master. Access pipelining can be
applied to both read and write cycles by the Flash array.
