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Freescale Semiconductor MPC5632M Manual Download Page 795

MPC563XM Reference Manual, Rev. 1

Freescale Semiconductor

795

 

Preliminary—Subject to Change Without Notice

23.4.4.1

Host Side Atomic Access

Host side atomic accesses can be achieved by either of following ways:

•

for one parameter, the SPRAM should be accessed by 32-bit-wide data transfers to ensure 
coherency

•

for two parameters only, using the Coherent Dual Parameter Controller.

•

indirectly, for any number of parameters, by requesting microcode to coherently access SPRAM in 
its behalf. The host side atomicity problem becomes, then, a microengine side atomicity problem. 
Some methods that use this approach to achieve coherency are described in 

Section 23.5.3, 

“Multiple Parameter Coherency Methods

.”

23.4.4.2

Microengine Side Atomic Accesses

23.4.4.2.1

Microengine Single Parameter Atomicity

SPRAM should be accessed by 32-bit-wide data transfers to ensure atomicity for 32-bit parameters. This 
applies either to Host-Microengine coherency or Microengine-Microengine coherency in a dual eTPU 
Engine system.

23.4.4.2.2

Microengine Dual Parameter Atomicity

Microengine has the ability to access two parameters coherently in back-to-back accesses, at random 
addresses: once it accesses SPRAM, it has priority over Host for another access in the next microcycle (see 

Section 23.4.4.5, “SPRAM Arbitration

”). Note that it applies 

only to Microengine-Host coherency

. For 

Microengine-Microengine coherency in a dual eTPU Engine system, one must use Hardware Semaphores 
(see 

Section 23.4.4.4, “Hardware Semaphores

”).

Microengine dual back-to-back accesses are guaranteed to be atomic in relation to Host Skyblue accesses 
or Coherent Dual-parameter Controller, regardless of semaphore usage: Host or CDC accesses cannot 
break-up a back-to-back Microengine access, neither Microengine can break a CDC transfer, due to the 
SPRAM arbitration mechanism described in 

Section 23.4.4.5, “SPRAM Arbitration

”.

Atomicity is not guaranteed if microengine enters halt state in the middle of a back-to-back access (see 

Section 23.4.10.2.2, “Microengine Halt State

”): Host can access SPRAM while microengine is halted in 

the middle of a back-to-back access.

23.4.4.2.3

Microengine Side Multiple Atomicity

Hardware Semaphores must be used for Microengine-Microengine coherency (more than 1 parameter) 
since two or more accesses from one Microengine are not atomic with respect to the other.

For multiple Microengine-Host coherency, the software methods described in 

Section 23.5.3, “Multiple 

Parameter Coherency Methods

,” or similar ones, must be used. Some of these methods rely on the fact that 

parameter access of a thread is atomic in relation to another thread in the same Engine, since a thread 
cannot be suspended (preempted).

For 1 parameter coherent access, or dual parameter coherency between only one Microengine and Host, 
the alternatives shown in previous sections apply.

Summary of Contents for MPC5632M

Page 1: ... Reference Manual Rev 1 Freescale Semiconductor 1 Preliminary Subject to Change Without Notice MPC563XM Microcontroller Reference Manual Devices Supported MPC5634M MPC5633M MPC5632M MPC563XRM Rev 1 25 Jul 2008 ...

Page 2: ...MPC563XM Reference Manual Rev 1 2 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 3: ... 39 1 4 7 Calibration EBI 40 1 4 8 SIU 41 1 4 9 ECSM 41 1 4 10 Flash 42 1 4 11 SRAM 43 1 4 12 BAM 43 1 4 13 eMIOS 43 1 4 14 eTPU 44 1 4 15 eQADC 46 1 4 16 DSPI 48 1 4 17 eSCI 50 1 4 18 FlexCAN 51 1 4 19 System Timers 52 1 4 20 Software Watchdog Timer SWT 53 1 4 21 Nexus Port Controller 53 1 4 22 JTAG 55 Chapter 2 Memory Map 2 1 Introduction 57 2 2 Memory Map 57 Chapter 3 Signal Descriptions 3 1 De...

Page 4: ... 4 5 1 Power on Reset 98 4 5 2 External Reset 98 4 5 3 Loss of Lock 98 4 5 4 Loss of Clock 99 4 5 5 Watchdog Timer Debug Reset 99 4 5 6 Software Watchdog Timer Reset 99 4 5 7 Checkstop Reset 100 4 5 8 JTAG Reset 100 4 5 9 Software System Reset 100 4 5 10 Software External Reset 101 4 6 Reset Registers in the SIU 101 4 7 Reset Configuration 101 4 7 1 Reset Configuration Half Word RCHW 101 4 7 2 Res...

Page 5: ...1 DMA Microarchitecture 151 7 4 2 DMA Basic Data Flow 152 7 4 3 DMA Performance 155 7 5 Initialization Application Information 158 7 5 1 DMA Initialization 158 7 5 2 DMA Programming Errors 159 7 5 3 DMA Arbitration Mode Considerations 160 7 5 4 DMA Transfer 161 7 5 5 TCD Status 164 7 5 6 Channel Linking 165 7 5 7 Dynamic Programming 166 7 5 8 Hardware Request Release Timing 167 Chapter 8 Multi Lay...

Page 6: ...IDGE Signal Description 201 9 5 PBRIDGE Functional Description 202 9 5 1 Read Cycles 202 9 5 2 Write Cycles 202 9 6 PBRIDGE Registers 202 Chapter 10 Flash Memory C90FL 10 1 Introduction 203 10 2 Platform Flash PFlash Memory Controller 203 10 2 1 Controller Overview 203 10 2 2 Features 203 10 2 3 Modes of Operation 204 10 2 4 Block Diagram 204 10 2 5 Signal Description 204 10 2 6 Functional Descrip...

Page 7: ...uffer Miss 280 11 7 4 Read Cycles Buffer Hit 280 11 7 5 Write Cycles 280 11 7 6 Error Termination 280 11 7 7 Access Pipelining 281 11 7 8 Flash Error Response Operation 281 11 7 9 Bank0 Page Read Buffers and Prefetch Operation 281 11 7 10Read While Write Functionality 283 11 7 11Wait State Emulation 284 11 7 12Flash Memory Array User Mode 285 Chapter 12 General Purpose Static RAM SRAM 12 1 Overvie...

Page 8: ... Initialization Application Information 397 13 6 1 Booting from External Memory 397 13 6 2 Running with SDR Single Data Rate Burst Memories 397 13 6 3 Running with Asynchronous Memories 398 13 6 4 Connecting an MCU to Multiple Memories 400 13 6 5 Address Decoding Example for External Master Accesses 401 13 6 6 EBI Operation with Reduced Pinout MCUs 402 13 6 7 Address Data Multiplexing Connection E...

Page 9: ...6 1 Interrupt Request Sources 425 14 6 2 Priority Management 426 14 6 3 Handshaking with Processor 428 14 6 4 Reserved Spaces in Memory Map 431 14 7 Initialization Application Information 432 14 7 1 Initialization Flow 432 14 7 2 Interrupt Exception Handler 432 14 7 3 Code Compression s Impact on Vector Table 434 14 7 4 ISR RTOS and Task Hierarchy 434 14 7 5 Order of Execution 434 14 7 6 Priority ...

Page 10: ...equest Enable Register SIU_DIRER 482 16 9 7 DMA Interrupt Request Select Register SIU_DIRSR 483 16 9 8 Overrun Status Register SIU_OSR 484 16 9 9 Overrun Request Enable Register SIU_ORER 484 16 9 10IRQ Rising Edge Event Enable Register SIU_IREER 485 16 9 11External IRQ Falling Edge Event Enable Register SIU_IFEER 485 16 9 12External IRQ Digital Filter Register SIU_IDFR 486 16 9 13Pad Configuration...

Page 11: ...559 17 4 2 Register Descriptions 560 17 5 Functional Description 569 17 5 1 Input Clock Frequency 569 17 5 2 Clock Configuration 569 17 5 3 Lock Detection 570 17 5 4 Loss of Clock Detection 570 17 5 5 Frequency Modulation 574 Chapter 18 Error Correction Status Module ECSM 18 1 Overview 577 18 2 Features 577 18 3 Module Memory Map 577 18 4 Register Descriptions 578 18 4 1 Platform ECC Registers 578...

Page 12: ...ew 607 21 2 Features 607 21 3 Modes of Operation 607 21 3 1 Normal Mode 607 21 3 2 Debug Mode 607 21 3 3 Internal Boot Mode 608 21 3 4 Serial Boot Mode 608 21 3 5 Calibration Bus Boot Mode 608 21 4 Memory Map 608 21 5 Functional Description 608 21 5 1 BAM Program Flow Chart 608 21 5 2 BAM Program Operation 609 21 5 3 Reset Configuration Half Word RCHW 611 21 5 4 Internal Boot Mode 613 21 5 5 Seria...

Page 13: ...TPU 23 1 Introduction 717 23 1 1 Overview 718 23 1 2 Features 723 23 1 3 Modes of Operation 727 23 2 External Signal Description 729 23 2 1 Overview 729 23 2 2 Detailed Signal Descriptions 730 23 3 Memory Map Register Definition 731 23 3 1 Memory Map 731 23 3 2 System Configuration Registers 735 23 3 3 Time Base Registers 745 23 3 4 Engine Related Registers 750 23 3 5 Channel Registers Layout 752 ...

Page 14: ... 958 24 2 1 Module Overview 958 24 2 2 Block Diagram 959 24 2 3 Features 960 24 3 Modes of Operation 962 24 3 1 Normal Mode 962 24 3 2 Streaming Mode 962 24 3 3 Debug Mode 963 24 3 4 Stop Mode 964 24 3 5 Factory Test Mode 965 24 4 External Signal Description 965 24 4 1 Overview 965 24 4 2 Detailed Signal Descriptions 968 24 5 Memory Map Register Definition 971 24 5 1 EQADC Memory Map 971 24 5 2 EQ...

Page 15: ...17 25 4 1 Decimation Filter Memory Map for SoC Integration 1117 25 4 2 Decimation Filter Registers Description 1119 25 4 3 Decimation Filter Memory Map for Parallel Side Interface 1127 25 4 4 PSI Register Description 1127 25 5 Functional Description 1129 25 5 1 Overview 1129 25 5 2 Parallel Side Interface PSI Description 1129 25 5 3 Input Buffer Description 1131 25 5 4 Output Buffer Description 11...

Page 16: ...1176 26 5 2 Start and Stop of DSPI Transfers 1178 26 5 3 Serial Peripheral Interface SPI Configuration 1179 26 5 4 Deserial Serial Interface DSI Configuration 1182 26 5 5 Combined Serial Interface CSI Configuration 1187 26 5 6 DSPI Baud Rate and Clock Delay Generation 1190 26 5 7 Transfer Formats 1193 26 5 8 Continuous Serial Communications Clock 1200 26 5 9 Timed Serial Bus TSB 1201 26 5 10Interr...

Page 17: ...pecific to This Device 1267 28 1 1 Device Specific Features 1267 28 2 Introduction 1267 28 2 1 Overview 1268 28 2 2 FlexCAN Module Features 1269 28 2 3 Modes of Operation 1270 28 3 External Signal Description 1271 28 3 1 Overview 1271 28 3 2 Signal Descriptions 1271 28 4 Memory Map Register Definition 1271 28 4 1 FlexCAN Memory Mapping 1272 28 4 2 Message Buffer Structure 1273 28 4 3 Rx FIFO Struc...

Page 18: ...1325 29 6 2 Interrupts 1326 29 7 Initialization and Application Information 1327 29 7 1 Example Configuration 1327 Chapter 30 Power Management Controller PMC 30 1 Introduction 1329 30 1 1 Block Diagram 1330 30 2 External Signal Description 1331 30 2 1 Detailed Signal Descriptions 1331 30 3 Memory Map Register Definition 1332 30 3 1 Configuration and Status Register CFGR 1332 30 3 2 Trimming Regist...

Page 19: ...Reset Configuration 1356 31 5 2 IEEE 1149 1 2001 JTAG Test Access Port 1356 31 5 3 TAP Controller State Machine 1356 31 5 4 JTAGC Block Instructions 1358 31 5 5 Boundary Scan 1360 31 6 Initialization Application Information 1360 Chapter 32 Nexus Port Controller NPC 32 1 Information Specific to This Device 1363 32 1 1 Parameter Values 1363 32 1 2 Unavailable Features 1363 32 1 3 Available Features ...

Page 20: ...nge Without Notice 32 5 4 Nexus JTAG Port Sharing 1380 32 5 5 MCKO and ipg_sync_mcko 1380 32 5 6 EVTO Sharing 1380 32 5 7 Nexus Reset Control 1380 32 5 8 System Clock Locked Indication 1380 32 6 Initialization Application Information 1381 32 6 1 Accessing NPC tool mapped registers 1381 ...

Page 21: ...ded for system software and hardware developers and applications programmers who want to develop products with the MPC563XM device It is assumed that the reader understands operating systems microprocessor system design basic principles of software and hardware and basic details of the Power Architecture Chapter Organization and Device Specific Information This document includes chapters that desc...

Page 22: ...MPC563XM Reference Manual Rev 1 22 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 23: ...s lower end powertrain applications 1 2 MPC563XM Device Summary Table 1 1 summarizes the MPC563XM family of microcontrollers Table 1 1 MPC563XM Device Summary Feature MPC5634M MPC5633M MPC5632M Flash memory size KB 1536 10241 768 RAM size KB 94 64 48 Processor core 32 bit e200z335 32 bit e200z335 32 bit e200z335 Core frequency MHz 40 60 80 40 60 80 40 60 Calibration bus width2 16 bits 16 bits DMA ...

Page 24: ...hannels Temperature sensor Yes Yes Yes Windowing software watchdog Yes Yes Yes Packages 144 LQFP 176 LQFP 208 MAPBGA 144 LQFP 176 LQFP5 208 MAPBGA 144 LQFP 176 LQFP 208 MAPBGA 1 Revision 1 of this device contains C90FL flash memory revision 2 of this device contains LC flash memory 2 Calibration package only 3 One FlexCAN module has 64 message buffers the other has 32 message buffers 4 165 interru...

Page 25: ...M SIU Calibration Interface eDMA Reset Control 24 KB Interrupt External IMUX GPIO Engine JTAG Nexus RAM 14 KB 3 KB 2x ADCI eTPU Crossbar Switch Pad Control JTAG Port Nexus Port Analog Vstby e200z335 Interrupt Blocks eDMA 64 bit SPE 16 Ch DSPIs eMIOS Controller 2x CANs 32 Ch AMUX ADC Bus 3 x 4 BAM 24KB S M M S S eQADC NEXUS 1 Peripheral Bridge Peripheral Requests from Interrupt Request Interrupt Re...

Page 26: ...ous serial communications with peripheral devices and other microcontroller units eTPU enhanced time processor unit channels Processes real time input events performs output waveform generation and accesses shared data without host intervention FlexCAN controller area network Supports the standard CAN communications protocol FMPLL frequency modulated phase locked loop Generates high speed system c...

Page 27: ...3 3 V Unused pins configurable as GPIO or timed I O Designed with EMI reduction techniques Phase locked loop Frequency modulation of system clock frequency On chip bypass capacitance Selectable slew rate and drive strength High performance e200z335 core processor 32 bit Power Architecture Book E programmer s model Variable Length Encoding Enhancements Allows PowerPC instruction set to be optionall...

Page 28: ...l compliment of vector scalar integer and floating point arithmetic operations including integer vector MAC MUL operations SIMD Provides rich array of extended 64 bit loads and stores to from extended GPRs Fully code compatible with e200z6 core Floating point IEEE 754 compatible with software wrapper Scalar single precision in hardware double precision with software library Conversion instructions...

Page 29: ...ing Phase locked loop FMPLL Reference clock pre divider PREDIV for finer frequency synthesis resolution Reduced frequency divider RFD for reducing the FMPLL output clock frequency without forcing the FMPLL to re lock System clock divider SYSDIV for reducing the system clock frequency in normal or bypass mode Input clock frequency range from 4 MHz to 20 MHz before the pre divider and from 4 MHz to ...

Page 30: ...r pin basis Pin function selection Configurable weak pull up or pull down Drive strength Slew rate Hysteresis System reset monitoring and generation External interrupt inputs filtering and control Critical Interrupt control Non Maskable Interrupt control Internal multiplexer subblock IMUX Allows flexible selection of eQADC trigger inputs eTPU Plus eMIOS and external signals Allows selection of int...

Page 31: ...ution from external memory on the calibration bus Download and execution of code via FlexCAN or eSCI Periodic interrupt timer PIT 32 bit wide down counter with automatic reload 4 channels clocked by system clock 1channel clocked by crystal clock Each channel can produce periodic software interrupt Each channel can produce periodic triggers for eQADC queue triggering 1 channel out of the 5 can be u...

Page 32: ...gle clock hardware support Nexus Class 1 Debug support Enhancements to make DMA and interrupt operation more flexible New programmable channel mode for increased flexibility of channel hardware Enhanced queued A D converter eQADC 2 independent on chip RSD Cyclic ADCs 8 10 and 12 bit Resolution Targets up to 10 bit accuracy at 500 KSample s ADC_CLK 7 5 MHz and 8 bit accuracy at 1 MSample s ADC_CLK ...

Page 33: ...ger modes to arm a particular CFIFO Generates interrupt when command coherency is not achieved External Hardware Triggers Supports rising edge falling edge high level and low level triggers Supports configurable digital filter Supports four external 8 to 1 muxes which can expand the input channel number from 31 to 59 2 deserial serial peripheral interface modules DSPI SPI Full duplex communication...

Page 34: ...uffer number Listen only mode capabilities Programmable clock source system clock or oscillator clock Message buffers may be configured as mailboxes or as FIFO Nexus port controller NPC Per IEEE ISTO 5001 2003 Real time development support for PowerPC core and eTPU Plus engine through Nexus class 2 1 Read and write access Nexus class 3 feature that is supported on this device Run time access of en...

Page 35: ... CLZ a 32x32 Hardware Multiplier array result feed forward hardware and support hardware for division Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions A Count Leading Zeros unit operates in a single clock cycle The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of fl...

Page 36: ...Multiply Accumulate MAC and dual integer multiply MUL in a pipelined fashion The general purpose register file is enhanced such that all 32 of the GPRs are extended to 64 bits wide and are used for source and destination operands thus there is a unified storage model for 32 x 32 MAC operations which generate greater than 32 bit results The majority of both scalar and vector operations including MA...

Page 37: ...granted access to a slave port in round robin fashion based upon the ID of the last master to be granted access The crossbar provides the following features 3 master ports e200z335 core complex Instruction port e200z335 core complex Load Store port eDMA 4 slave ports FLASH calibration bus SRAM Peripheral bridge A B eTPU eMIOS SIU DSPI eSCI FlexCAN eQADC BAM decimation filter PIT STM and SWT 32 bit...

Page 38: ...hich ISR needs to be executed It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs To allow the appropriate priorities for each source of interrupt request the priority of each interrupt request is software configurable When multiple tasks share a resource coherent accesses to that resource need to be supported The INTC suppo...

Page 39: ...ck divider ratio are all software configurable The PLL has the following major features Input clock frequency from 4 MHz to 20 MHz Voltage controlled oscillator VCO range from 256 MHz to 512 MHz resulting in system clock frequencies from 16 MHz to 80 MHz with granularity of 4 MHz or better Reduced frequency divider RFD for reduced frequency operation without forcing the PLL to relock 3 modes of op...

Page 40: ...lowing features 22 bit address bus two most significant signals multiplexed with two chip selects 16 bit data bus Multiplexed mode with addresses and data signals present on the data lines NOTE The calibration EBI must be configured in multiplexed mode when the extended Nexus trace is used on the VertiCal This is because Nexus signals and address lines of the calibration bus share the same balls i...

Page 41: ...rnal pins Pad configuration control for each pad Pad configuration control for virtual I O via DSPI serialization System reset monitoring and generation Power on reset support Reset status register provides last reset source to software Glitch detection on reset input Software controlled reset assertion External interrupt 11 interrupt requests Rising or falling edge event detection Programmable di...

Page 42: ...fword word and doubleword reads are supported Only aligned word and doubleword writes are supported Fetch Accelerator Architected to optimize the performance of the flash with the CPU to provide single cycle random access to the flash up to 80 MHz system clock speed Configurable read buffering and line prefetch support Four line read buffers 128 bits wide and a prefetch controller Hardware and sof...

Page 43: ...he MPC563XM hardware accordingly The BAM provides the following features Sets up MMU to cover all resources and mapping all physical address to logical addresses with minimum address translation Sets up the MMU to allow user boot code to execute as either Classic Power Architecture Book E code default or as Freescale VLE code Detection of user boot code Automatic switch to serial boot mode if inte...

Page 44: ...ures 24 bit registers for captured match values 24 bit internal counter Global prescaler Selectable time base Can generate its own time base Three 24 bit wide counter buses Counter bus A can be driven by channel 23 Counter bus B and C are driven by channels 0 and 8 respectively Counter bus A can be shared among all channels Channels 0 to 6 and 8 to 15 can share counter buses B and C respectively c...

Page 45: ... for improved noise immunity Identical orthogonal channels each channel can perform any time function Each time function can be assigned to more than one channel as a given time so each signal can have any functionality Each channel has an event mechanism which supports single and double action functionality in various combinations It includes two 24 bit capture registers two 24 bit match register...

Page 46: ...ed queued analog to digital converter eQADC block provides accurate and fast conversions for a wide range of applications The eQADC provides a parallel interface to two on chip analog to digital converters ADC and a single master to single slave serial interface to an off chip external device Both on chip ADCs have access to all the analog channels The eQADC prioritises and transfers commands from...

Page 47: ...M sample second 8 bit conversion time 733 ns 1 4M sample second Up to 10 bit accuracy at 500 KSample s and 9 bit accuracy at 1 MSample s Differential conversions Single ended signal range from 0 to 5 V Variable gain amplifiers on differential inputs x1 x2 x4 Sample times of 2 default 8 64 or 128 ADC clock cycles Provides time stamp information when requested Parallel interface to eQADC CFIFOs and ...

Page 48: ...PI block provides a synchronous serial interface for communication between the MPC563XM MCU and external devices The DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory mapped registers The channels and register content are transmitted using a SPI like protocol This SPI like protocol is completely configurable for baud rate polarity and...

Page 49: ...bility into the TX and RX FIFOs for ease of debugging FIFO Bypass Mode for low latency updates to SPI queues Programmable transfer attributes on a per frame basis Parameterized number of transfer attribute registers from two to eight Serial clock with programmable polarity and phase Various programmable delays PCS to SCK delay SCK to PCS delay Delay between frames Programmable serial frame size of...

Page 50: ...apped register Transfer initiation conditions Continuous Edge sensitive hardware trigger Change in data Pin serialization deserialization with interleaved SPI frames for control and diagnostics Continuous serial communications clock Support for parallel and serial chaining of up to four DSPI blocks 1 4 17 eSCI The enhanced serial communications interface eSCI allows asynchronous serial communicati...

Page 51: ...FlexCAN module A contains 64 message buffers MB FlexCAN module C contains 32 message buffers The FlexCAN module provides the following features Based on and including all existing features of the Freescale TouCAN module Full Implementation of the CAN protocol specification Version 2 0B Standard data and remote frames Extended data and remote frames Zero to eight bytes data length Programmable bit ...

Page 52: ...des five independent timer channels capable of producing periodic interrupts and periodic triggers The PIT has no external input or output pins and is intended to be used to provide system tick signals to the operating system as well as periodic triggers for eQADC queues Of the five channels in the PIT four are clocked by the system clock one is clocked by the crystal clock This one channel is als...

Page 53: ...otected by a software key or a write once register 1 4 21 Nexus Port Controller The NPC Nexus Port Controller block provides real time development support capabilities for the MPC563XM PowerPC based MCU in compliance with the IEEE ISTO 5001 2003 standard This development support is supplied for MCUs without requiring external address and data pins for internal visibility The NPC block is an integr...

Page 54: ... mode interface Auxiliary Output port 1 MCKO message clock out pin 4 MDO message data out pins 2 MSEO message start end out pins 1 EVTO event out pin Auxiliary input port 1 EVTI event in pin 17 pin Full Port interface in VertiCal calibration package 3 3 V interface Auxiliary Output port 1 MCKO message clock out pin 4 or 12 MDO message data out pins 8 extra full port pins shared with calibration bu...

Page 55: ...er on reset status indication during reset via MDO 0 in disabled and reset modes 1 4 22 JTAG The JTAGC JTAG Controller block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Testing is performed via a boundary scan technique as defined in the IEEE 1149 1 2001 standard All data input to and output from the JTAGC block i...

Page 56: ...or Preliminary Subject to Change Without Notice 64 bit Censorship password register If the external tool writes a 64 bit password that matches the Serial Boot password stored in the internal flash shadow row Censorship is disabled until the next system reset ...

Page 57: ...eTPU Code RAM 0xC3FD_0000 0xC3FD_3FFF FLASH Shadow Block 0x00FF_C000 0x00FF_FFFF Reserved 0xC3FD_4000 0xFBFF_FFFF Emulation reMapping of Flash 0x0100_0000 0x1FFF_FFFF Reserved 0xFC00_0000 0xFFEF_FFFF Reserved 0x2000_0000 0x2FFF_FFFF e200 Platform Peripherals XBAR SWT STM ECSM eDMA and INTC 0xFFF0_0000 0xFFF7_FFFF Calibration Memory Space 0x3000_0000 0x3FFF_FFFF SRAM 94 KB 2 0x4000_0000 0x4001_77FF...

Page 58: ...devices 2 See Table 2 3 for the value of other family devices Table 2 2 Detailed MPC5634M Memory Map Address Range1 Allocated Size bytes Used Size bytes Use 0x0000_0000 0x0017_FFFF 1 5 M 1 5 M Flash Memory Array2 0x0018_0000 0x00FF_BFFF 14 5 M 16K N A Reserved 0x00FF_C000 0x00FF_FFFF 16 K 16 K Flash Memory Shadow Block 0x0100_0000 0x1FFF_FFFF 496 M 1 M Emulation Remapping of Flash Memory Array 0x2...

Page 59: ...000 0xC3FE_3FFF 16 K N A Reserved 0xC3FE_4000 0xC3FE_7FFF 16 K N A Reserved 0xC3FE_8000 0xC3FE_BFFF 16 K N A Reserved 0xC3FE_C000 0xC3FE_FFFF 16 K N A Reserved 0xC3FF_0000 0xC3FF_3FFF 16 K N A PIT RTI 0xC3FF_4000 0xC3FF_7FFF 16 K N A Reserved 0xC3FF_8000 0xC3FF_BFFF 16 K N A Reserved 0xC3FF_C000 0xC3FF_BFFF 16 K N A Not Allocated 0xC400_0000 0xDFFF_FFFF 512 M 64 M N A Reserved Bridge Peripherals M...

Page 60: ...FFF 16 K N A Not Allocated 0xFFF8_0000 0xFFF8_3FFF 16 K 164 Enhanced Queued Analog to Digital Converter eQADC_A 0xFFF8_4000 0xFFF8_7FFF 16 K N A Reserved 0xFFF8_8000 0xFFF8_BFFF 16 K 4 K Decimation Filter A 0xFFF8_C000 0xFFF8_FFFF 16 K N A Reserved 0xFFF9_0000 0xFFF9_3FFF 16 K N A Reserved 0xFFF9_4000 0xFFF9_7FFF 16 K 200 Deserial Serial Peripheral Interface DSPI_B 0xFFF9_8000 0xFFF9_BFFF 16 K 200...

Page 61: ... 0xFFFF_4000 0xFFFF_7FFF 16 K N A Not Allocated 0xFFFF_8000 0xFFFF_BFFF 16 K N A Reserved 0xFFFF_C000 0xFFFF_FFFF 16 K 4 K Boot Assist Module BAM 1 If allocated size used size then the base address for the block is the lowest address of the listed address range unless noted otherwise 2 See Table 2 3 for the value of other family devices 3 See Table 2 3 for the value of other family devices Table 2...

Page 62: ...MPC563XM Reference Manual Rev 1 62 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 63: ... Without Notice Chapter 3 Signal Descriptions This chapter describes signals that connect to package pins It includes pinout diagrams recommended system connections and detailed discussions of signals 3 1 Device Pin Assignments 3 1 1 144 LQFP Figure 3 1 shows the pinout of the 144 pin LQFP ...

Page 64: ...DEH4B EMIOS11 EMIOS12 EMIOS14 EMIOS23 CNTXA CNRXA PLLREF RXDB BOOTCFG WKPCFG TXDB 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 AN21 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 REFBYPC VRH VRL AN22 AN23 AN24 AN25 AN27 AN28 AN30 AN31 AN32 AN33 AN34 AN35 VDD AN12 SDS AN13 SDO AN14 SDI AN15 FCK VSS MDO3 VDDEH7 MDO2 MDO1 MDO0 MSEO0 AN18 AN1...

Page 65: ...A29 ETPUA26 NC VDDEH6 TDO MCKO JCOMP G ETPUA24 ETPUA27 ETPUA25 ETPUA21 VSS VSS VSS VSS SOUTB PCSB3 SINB PCSB0 H ETPUA23 ETPUA22 ETPUA17 ETPUA18 VSS VSS VSS VSS NC PCSB4 PCSB2 PCSB1 J ETPUA20 ETPUA19 ETPUA14 ETPUA13 VSS VSS VSS VSS PCSB5 TXDA NC SCKB K ETPUA16 ETPUA15 ETPUA7 VDDEH1 VSS VSS VSS VSS CNTXC RXDA RSTOUT VDDRE G L ETPUA12 ETPUA11 ETPUA6 ETPUA0 TXDB CNRXC WKPCFG RESET M ETPUA10 ETPUA9 ETP...

Page 66: ...put GPIO I I I I O VDDEH6a PLLREF Up Up 496 208 144 BOOTCFG_ IRQ 3 _ ETRIG 1 _ GPIO 212 Boot Configuration Input External Interrupt Request eQADC Trigger Input GPIO I I I I O VDDEH6a BOOTCF G Down Down 496 208 144 WKPCFG_ NMI_ GPIO 213 Weak Pull Configuration Input Non Maskable Interruption GPIO I I I O VDDEH6a WKPCFG Up Up 496 208 144 Calibration 46 CAL_ADDR 12 15 Calibration Address Bus O VDDE12...

Page 67: ...ed CLKOUT Enabled 208 496 NEXUS 9 EVTI_ eTPU_A 2 _ GPIO 231 Nexus Event In eTPU A Channel GPIO I O I O VDDEH7 496 208 144 EVTO _ eTPU_A 4 _ GPIO 227 Nexus Event Out eTPU A Channel GPIO O O I O VDDEH7 I Up I Up 496 208 144 MCKO_ GPIO 219 Nexus Message Clock Out GPIO O I O VDDEH7 496 208 144 MDO 0 13_ eTPU_A 13 _ GPIO 220 Nexus Message Data Out eTPU A Channel GPIO O O I O VDDEH7 496 208 144 MDO 1 _ ...

Page 68: ...208 144 CNRX_A_ RXD_A_ GPIO 84 CAN_A Receive eSCI_A Receive GPIO I I I O VDDEH4b Up Up 496 208 144 CNTX_C_ GPIO 87 CAN_C Transmit GPIO O I O VDDEH6a Up Up 496 208 144 CNRX_C_ GPIO 88 CAN_C Receive GPIO I I O VDDEH6a Up Up 496 208 144 eSCI 4 TXD_A_ eMIOS 13 _ GPIO 89 eSCI_A Transmit eMIOS Channel GPIO O15 O I O VDDEH6a Up Up 496 208 144 RXD_A_ eMIOS 15 _ GPIO 90 eSCI_A Receive eMIOS Channel GPIO I ...

Page 69: ...O I O I O VDDEH6b Up Up 496 208 144 PCS_B 5 _ PCS_C 0 _ GPIO 110 DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select GPIO O I O I O VDDEH6b Up Up 496 208 144 eQADC 35 AN 0 DAN0 Single Ended Analog Input Positive Terminal Differential Input I I VDDA I AN 0 496 208 144 AN 1 DAN0 Single Ended Analog Input Negative Terminal Differential Input I I VDDA I AN 1 496 208 144 AN 2 DAN1 Single Ended ...

Page 70: ... _ ETPU_A 27 _ SDI Single Ended Analog Input Mux Address ETPU_A Channel eQADC Serial Data In I O O I VDDEH7 I AN 14 496 208 144 AN 15 _ FCK_ ETPU_A 29 Single Ended Analog Input eQADC Free Running Clock ETPU_A Channel I O O VDDEH7 I AN 15 496 208 144 AN 16 18 Single Ended Analog Input I VDDA I AN x 496 208 144 AN 21 25 Single Ended Analog Input I VDDA I AN x 496 208 144 AN 27 28 Single Ended Analog...

Page 71: ...WKPCFG WKPCFG 496 208 144 eTPU_A 8 _ eTPU_A 20 _ SOUT_B_LVDS _ GPIO 122 eTPU_A Channel eTPU_A Channel SOUT_B LVDS GPIO I O O O I O VDDEH4a WKPCFG WKPCFG 496 208 144 eTPU_A 9 _ eTPU_A 21 _ GPIO 123 eTPU_A Channel eTPU_A Channel GPIO I O O I O VDDEH4a WKPCFG WKPCFG 496 208 144 eTPU_A 10 11 _ eTPU_A 22 23 _ GPIO 124 125 eTPU_A Channel eTPU_A Channel GPIO I O O I O VDDEH1b WKPCFG WKPCFG 496 208 144 eT...

Page 72: ...nal External Interrupt Request eTPU_A Channel External GPIO I O I O I O VDDEH1a WKPCFG WKPCFG 496 208 144 eTPU_A 24 _ IRQ 12 _ SCK_C_LVDS _ GPIO 138 eTPU_A Channel External External Interrupt Request SCK_C LVDS GPIO O I I O I O VDDEH1a WKPCFG WKPCFG 496 208 144 eTPU_A 25 _ IRQ 13 _ SCK_C_LVDS _ GPIO 139 eTPU_A Channel External External Interrupt Request SCK_C LVDS GPIO O I I O I O VDDEH1a WKPCFG W...

Page 73: ...PCFG 496 208 144 eMIOS 8 9 _ eTPU_A 8 9 _ GPIO 187 188 eMIOS Channel eTPU_A Channel GPIO I O O I O VDDEH4b WKPCFG WKPCFG 496 208 144 eMIOS 10 11 _ GPIO 189 190 eMIOS Channel GPIO I O I O VDDEH4b WKPCFG WKPCFG 496 208 144 eMIOS 12 _ DSPI_C_SOUT eTPU_A 27 _ GPIO 191 eMIOS Channel DSPI C Data Output eTPU_A Channel GPIO O O O I O VDDEH4b WKPCFG WKPCFG 496 208 144 eMIOS 14 _ IRQ 0 _ eTPU_A 29 _ GPIO 19...

Page 74: ...Supply I VDDREG 5 0V I 496 208 144 VDD x4 Internal Logic Supply Input I VDD 1 2V I 496 208 144 VSS x4 Ground VSS0 I 496 208 144 VDDEH1a VDDEH1b I O Supply Input I VDDEH122 3 3V 5 0V I 496 208 144 VSSE1a VSSE1b I O Ground Input I VSSEH1 496 208 144 VDDEH4a VDDEH4b I O Supply Input I VDDEH422 3 3V 5 0V I 496 208 144 VSSE4a VSSE4b I O Ground Input I VSSEH4 496 208 144 VDDEH6a23 VDDEH6b I O Supply Inp...

Page 75: ...is high 10 High when the pin is configured to Nexus low otherwise 11 O Low for the 496 package with NEXUSCFG 0 I Up otherwise 12 CAL_ADDR Low for the 496 package with NEXUSCFG 0 EVTI Up otherwise 13 If JCOMP is asserted during reset MDO 0 is driven high until the crystal oscillator becomes stable at which time it is then negated 14 TDI and TDO are required for JTAG operation 15 From the user point...

Page 76: ... function is the external trigger input for the eQADC 3 3 1 3 BOOTCFG_IRQ 3 _ETRIG 1 _GPIO 212 Reset Configuration External Interrupt Request eQADC Trigger Input GPIO BOOTCFG_IRQ 3 _ETRIG 1 _GPIO 213 are sampled on the negation of the RSTOUT pin The values are used by the BAM program to determine the boot configuration of this device The alternate function is an external interrupt request input Th...

Page 77: ... 0 15 Calibration Data CAL_DATA 0 15 are the calibration data signals 3 3 2 8 CAL_OE Calibration Output Enable CAL_OE indicates that the calibration interface is ready to accept read data 3 3 2 9 CAL_RD_WR Calibration Read Write CAL_RD_WR indicates whether a calibration bus transfer is a read or write operation 3 3 2 10 CAL_TS_ALE Calibration Transfer Start Address Latch Enable The Calibration Tra...

Page 78: ... that provides timing to a development tool for a single watchpoint or breakpoint occurrence The alternate functions are output channel for eTPU_A 4 module and GPIO 227 3 3 3 4 MCKO CLKOUT_GPIO 219 Nexus Message Clock Out CLKOUT GPIO MCKO is a free running clock output to the development tools which is used for timing of the MDO and MSEO signals The alternate functions is GPIO 219 when package QFP...

Page 79: ...d GPIO 224 3 3 3 10 MSEO 1 _eTPU_A 29 _GPIO 225 Nexus Message Start End Out eTPU_A Channel GPIO Is the output that indicates when messages start and end on the MDO pins The alternate functions are output channel for eTPU_A 29 module and GPIO 225 3 3 4 JTAG 3 3 4 1 TCK JTAG Test Clock Input TCK provides the clock input for the on chip test logic 3 3 4 2 TDI_eMIOS 5 _GPIO 232 JTAG Test Data Input TD...

Page 80: ...ternate function is not implemented 3 3 5 4 CNRX_C_GPIO 88 CAN_C Receive GPIO CNRX_C_GPIO 88 is the receive pin for the FlexCAN C module The first alternate function is not implemented 3 3 6 eSCI 3 3 6 1 TXD_A_eMIOS 13 _GPIO 89 eSCI_A Transmit eMIOS Channel GPIO TXD_A_eMIOS 13 _GPIO 89 is the transmit pin for the eSCI A module Its alternate function is eMIOS 13 channel output pin 3 3 6 2 RXD_A_eMI...

Page 81: ... DSPI B module Its first alternate function is not implemented 3 3 7 5 PCS_B 1 _GPIO 106 DSPI_B Chip Select GPIO PCS_B 1 _GPIO 106 is a peripheral chip select output pin for the DSPI B module Its first alternate function is not implemented 3 3 7 6 PCS_B 2 _SOUT_C_GPIO 107 DSPI_B Chip Select GPIO PCS_B 2 _SOUT_C_GPIO 107 is a peripheral chip select output pin for the DSPI B module The alternate fun...

Page 82: ...e positive terminal input of the differential analog input DAN1 3 3 8 4 AN 3 _DAN1 Analog Input Differential Analog Input Negative Terminal AN 3 is a single ended analog input pin DAN1 is the negative terminal input of the differential analog input DAN1 3 3 8 5 AN 4 _DAN2 Analog Input Differential Analog Input Positive Terminal AN 4 is a single ended analog input pin DAN2 is the positive terminal ...

Page 83: ...plexed Analog Input Analog Input AN 10 and AN 39 are single ended analog input pins ANY is a single ended analog input to one of the on chip ADCs in external multiplexed mode 3 3 8 12 AN 11 _ANZ Analog Input External Multiplexed Analog Input AN 11 is a single ended analog input pin ANZ is a single ended analog input to one of the on chip ADCs in external multiplexed mode 3 3 8 13 AN 12 _MA 0 _eTPU...

Page 84: ...A 29 is a single ended analog input pin The first alternate function is the free running clock for the eQADC SSI The second alternate function is the eTPU 29 channel output pin 3 3 8 17 AN 16 18 Analog Input AN 16 18 are single ended analog input pins 3 3 8 18 AN 21 25 Analog Input AN 21 25 are single ended analog input pins 3 3 8 19 AN 27 28 Analog Input AN 27 28 are single ended analog input pin...

Page 85: ... 9 4 eTPU_A 6 _eTPU_A 18 _SCK_B_LVDS _GPIO 120 eTPU_A Channel eTPU_A Channel SCK_B_LVDS GPIO eTPU_A 6 _eTPU_A 18 _SCK_B_LVDS _GPIO 120 is input output channel pin for the eTPU_A module The alternate function is the output channel pin for the eTPU_A LVDS output for DSPI B clock 3 3 9 5 eTPU_A 7 _eTPU_A 19 _SOUT_B_LVDS _eTPU_A 6 _GPIO 121 eTPU_A Channel eTPU_A Channel SOUT_B_LVDS eTPU_A Channel GPIO...

Page 86: ...DSPI B module output channel pin for the eTPU_A 3 3 9 11 eTPU_A 15 _PCS_B 5 _GPIO 129 eTPU_A Channel DSPI_B Chip Select GPIO eTPU_A 15 _PCS_B 5 _GPIO 129 is an input output channel pin for the eTPU_A module The alternate function is a peripheral chip select for the DSPI B module 3 3 9 12 eTPU_A 16 _GPIO 130 eTPU_A Channel GPIO eTPU_A 16 _GPIO 130 is an input output channel pin for the eTPU_A modul...

Page 87: ...n for the eTPU_A module The alternate function is external interrupt request inputs for the SIU module LVDS output for DSPI C clock 3 3 9 20 eTPU_A 25 _IRQ 13 _SCK_C_LVDS _GPIO 139 eTPU_A Channel Output Only External Interrupt eTPU_A Channel SCK_C_LVDS GPIO eTPU_A 25 _IRQ 13 _SCK_C_LVDS _GPIO 139 is output channel pin for the eTPU_A module The alternate function is external interrupt request input...

Page 88: ...ect for the DSPI C module output channel pin for the eTPU_A 11 3 3 9 26 eTPU_A 31 _PCS_C 4 _eTPU_A 13 _GPIO 145 eTPU_A Channel DSPI_C Chip Select eTPU_A Channel Output Only GPIO eTPU_A 31 _PCS_C 4 _GPIO 145 is an input output channel pin for the eTPU_A module The alternate function is a peripheral chip select for the DSPI C module output channel pin for the eTPU_A 31 3 3 10 eMIOS 3 3 10 1 eMIOS 0 ...

Page 89: ... 10 7 eMIOS 14 _IRQ 0 _eTPU_A 29 _GPIO 193 eMIOS Channel Input Output External Interrupt eTPU_A Channel Output Only GPIO eMIOS 14 _IRQ 0 _eTPU_A 29 _GPIO 193 is an eMIOS 14 channel input output pin The alternate function is external interrupt request input for the SIU module output channel pin for the eTPU_A 29 and GPIO 193 3 3 10 8 eMIOS 23 _GPIO 202 eMIOS Channel eMIOS 23 _GPIO 202 is an eMIOS 2...

Page 90: ...2 5 VDD33 Voltage Regulator Control Bypass Capacitor VDD33 is the input pin for the bypass capacitor of the 3 3V voltage regulator This pin is used on 208 and 496 pin packages instead of VRC33 3 3 12 6 VRCCTL Voltage Regulator Control Output VRCCTL is the output pin for the on chip 1 2 V regulator control circuit 3 3 12 7 VDDA0 1 Voltage Reference High VDDA0 1 are the analog supply input pins for ...

Page 91: ...ckages 3 3 12 15 VDDE7 I O Supply Input VDDE7 is the 1 8 V to 3 3 V 5 I O supply input pin to the I O segment 7 It is only used on the 208 pin package Segment 7 on the 208 pin package is equivalent to segment 12 in the 496 pin package 3 3 12 16 VDDEH9 I O Supply Input VDDEH9 is the 3 3 V to 5 0V 5 supply input pin to the I O segment 9 It is only used on the 208 pin package Segment 9 on the 208 pin...

Page 92: ...MPC563XM Reference Manual Rev 1 92 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 93: ...ddition the FMPLL defaults to bypass mode with the system clock being supplied directly by the clock reference dictated by the PLLREF pin The Reset Status Register SIU_RSR gives the source or sources of the last reset and indicates whether a glitch has occurred on the RESET pin The SIU_RSR is updated for all reset sources except JTAG reset All reset sources initiate execution of the Boot Assist Mo...

Page 94: ...ks in duration that fall below the switch point of the input buffer logic of the VDDEH input pins The switch point lies between the maximum VIL and minimum VIH specifications for the VDDEH input pins 4 3 2 RSTOUT The RSTOUT pin is an active low output that uses a push pull configuration The RSTOUT pin is driven to the low state by the MCU for all internal and external reset sources Depending on th...

Page 95: ... perceived to be of good quality The time it takes for the crystal oscillator to stabilize is in addition to those indicated in Table 4 1 4 5 Reset Source Descriptions For the following reset source descriptions refer to the reset flow diagrams in Figure 4 1 and Figure 4 2 Figure 4 1 shows the reset flow for assertion of the RESET pin Figure 4 2 shows the internal processing of reset for all reset...

Page 96: ...onductor Preliminary Subject to Change Without Notice Figure 4 1 External Reset Flow Diagram Asserted F T RESET F T Asserted RESET Asserted RESET A Wait 2 Clock Cycles Set Latch Wait 8 Clock Set RGF Bit To entry point in internal reset flow F T Cycles ...

Page 97: ...oftware System Reset F T F T Clock Cycles Clock Cycles F T Latch WKPCFG Pin Latch PLLREF BOOTCFG Reset Request RSTOUT Negate Internal Resets and Wait CNT1 Wait 4 Clock Cycles Wait CNT1 Apply WKPCFG Pin RSTOUT Assert Internal Resets and A Entry point from Values Asserted Internal Reset F T Crystal Stable external reset flow and POR NOTES 1 The clock count CNT depends on the reset source and type of...

Page 98: ... PLLREF 0 the clock is released to the system immediately When the clock is stable and released to the chip the reset controller counts a predetermined number of clock cycles refer to Section 4 3 2 RSTOUT before negating the RSTOUT pin The WKPCFG and BOOTCFG pins are sampled 4 clock cycles before the negation of RSTOUT and the associated bits fields are updated in the SIU_RSR In addition the PORS ...

Page 99: ...and a time out occurs with the Enable Next Watchdog Timer EWT and Watchdog Timer Interrupt Status WIS bits set in the Timer Status Register and with the Watchdog Reset Control WRC field in the Timer Control Register configured for a reset The WDRS bit in the SIU_RSR is also set when a debug reset command is issued from a debug tool To determine whether the WDRS bit was set due to a Watchdog Timer ...

Page 100: ... reset status bits in the SIU_RSR are cleared Refer to the e200z335 Core Reference Manual for more information 4 5 8 JTAG Reset A system reset occurs when JTAG is enabled and either the EXTEST CLAMP or HIGHZ instructions are executed by the JTAG controller The internal reset signal is asserted The state of the RSTOUT pin is determined by the JTAG instruction The value on the WKPCFG pin is applied ...

Page 101: ...gration Unit SIU on this device includes two registers SIU_RSR and SIU_SRCR that affect the reset behavior of this device See Chapter 16 System Integration Unit SIU for descriptions of these registers 4 7 Reset Configuration 4 7 1 Reset Configuration Half Word RCHW 4 7 1 1 RCHW Overview The Reset Configuration Half Word RCHW is a collection of control bits from various internal registers that spec...

Page 102: ...and TBL to 0x0000_0000_0000_0000 and enables the e200z335 core Watchdog Timer with a time out period of 3 x 217 system clock cycles Example For 8 MHz crystal 12 MHz system clock 32 7mS time out For 20MHz crystal 30 MHz system clock 13 1 mS time out 0 BAM program does not write the e200z335 timebase registers TBU and TBL nor enable the e200z335 core Watchdog Timer VLE VLE Indicator This bit is used...

Page 103: ...e BOOTCFG WKPCFG and PLLREF pin for a power on reset The timing diagram is also valid for internal external resets assuming that VDD and VDD33 are within valid operating ranges The value of the PLLREF pin is latched at the negation of the RSTOUT pin The value of the WKPCFG signal is applied at the assertion of the internal reset signal assertion of RSTOUT The values of the WKPCFG and BOOTCFG pins ...

Page 104: ... is applied at the assertion of the internal reset signal assertion of RSTOUT If the WKPCFG signal is logic high at this time pull up devices will be enabled on the eTPU and eMIOS pins If the WKPCFG signal is logic low at the assertion of the internal reset signal pull down devices will be enabled on those pins The value on WKPCFG must be held constant during reset to avoid oscillations on the eTP...

Page 105: ...t State in Chapter 23 Enhanced Time Processing Unit eTPU See the Modes of Operation section of the individual module for a description of how the Debug Mode affects the behavior of the module 5 2 3 Low Power Modes This device can be configured such that the clock to some or all of the modules can be stopped to reduce the power consumption A tiered approach towards clock gating is implemented In th...

Page 106: ...he clock gating is centralized in the SIU_HLT register which has one control bit for each module to be halted The CPU itself can also be halted 5 2 3 3 Standby Mode In this mode the power is removed from all functions except the standby RAM Standby mode is entered by removing all power supplies except the one on the VSTBY pin The device is recovered from the standby mode when powered again see Cha...

Page 107: ...D MFD Lock Clock Quality Monitor Loss of Reference Loss of VCO PLLREF RC OSC FlexCAN x 2 MDIS CLK_SRC CAN Interface Message Buffer CLK Glitch Filter SIU MDIS CLK SIU_HLT DSPI x 2 EBI calibration eTPU CLKOUT CLKOUT Divider eMIOS one bit per peripheral MCKO MCKO Divider CPU XBAR DMA PBRIDGE RAM p_wakeup ipg_stop_ack ipg_stop_ack p_stop INTC eQADC Flash BAM STM ipg_stop ipg_stop 8 8 8 1 4 4 4 SWT ipg...

Page 108: ...FD MFD Lock Clock Quality Monitor Loss of Reference Loss of VCO PLLREF RC OSC FlexCAN x 2 MDIS CLK_SRC CAN Interface Message Buffer CLK Glitch Filter SIU MDIS CLK SIU_HLT DSPI x 2 EBI calibration eTPU CLKOUT CLKOUT Divider eMIOS one bit per peripheral MCKO MCKO Divider CPU XBAR DMA PBRIDGE RAM p_wakeup ipg_stop_ack ipg_stop_ack p_stop INTC eQADC Flash BAM STM ipg_stop ipg_stop 8 8 8 1 4 4 4 SWT ip...

Page 109: ...D MFD Lock Clock Quality Monitor Loss of Reference Loss of VCO PLLREF RC OSC FlexCAN x 2 MDIS CLK_SRC CAN Interface Message Buffer CLK Glitch Filter SIU MDIS CLK SIU_HLT DSPI x 2 EBI calibration eTPU CLKOUT CLKOUT Divider eMIOS one bit per peripheral MCKO MCKO Divider CPU XBAR DMA PBRIDGE RAM p_wakeup ipg_stop_ack ipg_stop_ack p_stop INTC eQADC Flash BAM STM ipg_stop ipg_stop 8 8 8 1 4 4 4 SWT ipg...

Page 110: ...roller Control Status Registers PLL PD PREDIV RFD MFD Lock Clock Quality Monitor Loss of Reference Loss of VCO PLLREF RC OSC FlexCAN x 2 MDIS CLK_SRC CAN Interface Message Buffer CLK Glitch Filter SIU MDIS CLK SIU_HLT DSPI x 2 EBI calibration eTPU CLKOUT CLKOUT Divider eMIOS one bit per peripheral MCKO MCKO Divider CPU XBAR DMA PBRIDGE RAM p_wakeup ipg_stop_ack ipg_stop_ack p_stop INTC eQADC Flash...

Page 111: ...ble in the 208 and 496 pin packages MCKO Nexus auxiliary port clock The oscillator clock can be selected as the clock source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance on the CAN bus 5 3 2 2 Software Controlled Power Management Software controlled power management and clock gating is supported on a peripheral by peripheral basis using a three tiered approa...

Page 112: ...re the EBI automatically disables the CLKOUT clock when there are no transactions on the external calibration bus The Flash array can be disabled by writing to a bit in the Flash memory map The modules that implement the MDIS function are listed in Table 5 1 along with the registers and bits that disable each module The software controlled clocks are enabled when the CPU comes out of reset Table 5...

Page 113: ...er to prevent accidental CPU halting a stop request is only activated if the CPU is in wait state due to the execution of the WAIT instruction indicated by the p_waiting signal The CPU recovers from the halted state when one of the following events happens A valid pending interrupt is detected by the core A request to enter debug mode is made by setting the DR bit in the OnCE control register OCR ...

Page 114: ...tem clock frequency The EBI supports gating of the CLKOUT signal when there are no external bus accesses in progress The hold time for external bus pins can be changed by writing to the external bus tap select EBTS bit in the SIU_ECCR NOTE The CLKOUT pin is only available in the 208 and 496 pin packages 5 3 2 3 3 Nexus Message Clock MCKO The Nexus message clock MCKO divider can be programmed to di...

Page 115: ...mbedded numerics operations using the general purpose registers All arithmetic instructions that execute in the core operate on data in the general purpose registers GPRs The GPRs have been extended to 64 bits in order to support vector instructions defined by the SPE APU These instructions operate on a vector pair of 16 bit or 32 bit data types and deliver vector and scalar results In addition to...

Page 116: ...on units Testability Synthesizeable full MuxD scan design ABIST MBIST for optional memory arrays 6 3 Location of Detailed Documentation Detailed documentation of the Z335 core is available as a separate document titled e200z3 Power ArchitectureTM Core Reference Manual This document is located on the Freescale Web site at http www freescale com files 32bit doc ref_manual e200z3RM pdf fsrch 1 ...

Page 117: ...Flag eQADC_FISR1_CFFF1 2 eQADC eQADC_FISR1 CFFF1 eQADC Command FIFO 1 Fill Flag eQADC_FISR1_RFDF1 3 eQADC eQADC_FISR1 RFDF1 eQADC Receive FIFO 1 Drain Flag eQADC_FISR2_CFFF2 4 eQADC eQADC_FISR2 CFFF2 eQADC Command FIFO 2 Fill Flag eQADC_FISR2_RFDF2 5 eQADC eQADC_FISR2 RFDF2 eQADC Receive FIFO 2 Drain Flag eQADC_FISR3_CFFF3 6 eQADC eQADC_FISR3 CFFF3 eQADC Command FIFO 3 Fill Flag eQADC_FISR3_RFDF3 ...

Page 118: ...CI_A Transmit SCI_A _RDRF_RXRDY 19 SCI_A SCISR1 RDRF SCI_A LINSTAT1 RXRDY SCI_A Receive Data EMIOSFLAG_F0 20 EMIOS EMIOSFLAG F0 eMIOS channel 0 Flag EMIOSFLAG_F1 21 EMIOS EMIOSFLAG F1 eMIOS channel 1 Flag EMIOSFLAG_F2 22 EMIOS EMIOSFLAG F2 eMIOS channel 2 Flag EMIOSFLAG_F3 23 EMIOS EMIOSFLAG F3 eMIOS channel 3 Flag EMIOSFLAG_F4 24 EMIOS EMIOSFLAG F4 eMIOS channel 4 Flag EMIOSFLAG_F8 25 EMIOS EMIOS...

Page 119: ...ing 16 32 and 64 channel implementations dependent on size of the TCD memory and design parameters Connections to the AMBA AHB crossbar switch for bus mastering the data movement slave bus for programming the module Parameterized support for 32 and 64 bit AMBA AHB datapath widths 32 byte transfer control descriptor per channel stored in local memory 32 bytes of data registers used as temporary sto...

Page 120: ...nel For all three methods one service request per execution of the minor loop is required Support for fixed priority and round robin channel arbitration Channel completion reported via optional interrupt requests One interrupt per channel optionally asserted at completion of major iteration count Error terminations are optionally enabled per channel and logically summed together to form a small nu...

Page 121: ...ed intmajor e_link 1 enable channel linking on major loop unsigned inte_sg 1 enable scatter gather descriptor unsigned intd_req 1 disable ipd_req when done unsigned intint_half 1 interrupt on citer biter 1 unsigned intint_maj 1 interrupt on major loop completion unsigned intstart 1 explicit channel start tcd transfer_control_descriptor where int refers to a 32 bit variable unless noted otherwise a...

Page 122: ...tware assertion of the tcd channel start bit the assertion of an enabled ipd_req from a device or the implicit assertion of a channel to channel link begin by reading the transfer control descriptor from the local RAM into the local dma_engine registers dma_engine read_from_local_memory channel dma_engine active 1 set active flag dma_engine done 0 clear done flag check the transfer control descrip...

Page 123: ...ual the dsize if the ssize dsize do a single read of source data number_of_source_reads xfer_size src_xfer_size for number_of_source_reads dma_engine data read_from_amba ahb dma_engine saddr src_xfr_size generate the next state source address sum the current saddr with the signed source offset ns_addr dma_engine saddr int dma_engine soff if enabled apply the power of 2 modulo to the next state add...

Page 124: ...ine bwc decrement the minor loop byte count dma_engine nbytes dma_engine nbytes xfr_size while dma_engine nbytes 0 end of minor inner loop dma_engine citer decrement major loop iteration count if the major loop is not yet exhausted update certain TCD values in the RAM if dma_engine citer 0 write_to_local_memory channel saddr dma_engine saddr write_to_local_memory channel daddr dma_engine daddr wri...

Page 125: ...consult Section 7 3 1 Register Descriptions and Section 7 4 Functional Description 7 3 Memory Map Register Definition The DMA s programming model is partitioned into two sections both mapped into the slave bus space the first region defines a number of registers providing control functions while the second region corresponds to the local transfer control descriptor memory Reading an unimplemented ...

Page 126: ...0x0104 DMA Channel 4 Priority DCHPRI4 DMA Channel 5 Priority DCHPRI5 DMA Channel 6 Priority DCHPRI6 DMA Channel 7 Priority DCHPRI7 0x0108 DMA Channel 8 Priority DCHPRI8 DMA Channel 9 Priority DCHPRI9 DMA Channel 10 Priority DCHPRI10 DMA Channel 11 Priority DCHPRI11 0x010c DMA Channel 12 Priority DCHPRI12 DMA Channel 13 Priority DCHPRI13 DMA Channel 14 Priority DCHPRI14 DMA Channel 15 Priority DCHP...

Page 127: ... In group fixed priority arbitration mode channel service requests in the highest priority group are executed first where priority level 3 is the highest and priority level 0 is the lowest The group priorities are assigned in the GRPnPri registers All group priorities must have unique values prior to any channel service requests occur otherwise a configuration error will be reported Unused group p...

Page 128: ... priority group arbitration is enabled GRP0PRI Channel Group 0 Priority Group 0 priority level when fixed priority group arbitration is enabled ERGA Enable Round Robin Group Arbitration 0 Fixed priority arbitration is used for selection among the groups 1 Round robin arbitration is used for selection among the groups ERCA Enable Round Robin Channel Arbitration 0 Fixed priority arbitration is used ...

Page 129: ...f the TCD citer e_link bit does not equal the TCD biter e_link bit All configuration error conditions except scatter gather and minor loop link error are reported as the channel is activated and assert an error interrupt request if enabled A scatter gather configuration error is reported when the scatter gather operation begins at major loop completion when properly enabled A minor loop channel li...

Page 130: ...rror 0 No channel priority error 1 The last recorded error was a configuration error in the channel priorities within a group All channel priorities within a group are not unique ERRCHN 5 0 Error Channel Number The channel number of the last recorded error excluding GPE and CPE errors SAE Source Address Error 0 No source address configuration error 1 The last recorded error was a configuration err...

Page 131: ...request flag does not affect a channel service request made explicitly through software or a linked channel request See Figure 7 4 and Table 7 5 for the DMAERQ definition NCE Nbytes Citer Configuration Error 0 No nbytes citer configuration error 1 The last recorded error was a configuration error detected in the TCD nbytes or TCD citer fields TCD nbytes is not a multiple of TCD ssize and TCD dsize...

Page 132: ...S C EEI registers are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read modify write sequence to the DMAEEI H L registers Register address DMA_Offset 0x0008 DMAERQH 0x000c DMAERQL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R ERQ 63 ERQ 62 ERQ 61 ERQ 60 ERQ 59 ERQ 58 ERQ 57 ERQ 56 ERQ 55 ERQ 54 ERQ 53 ERQ 52 ERQ 51 ERQ 50...

Page 133: ...dress DMA_Offset 0x0010 DMAEEIH 0x0014 DMAEEIL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R EEI6 3 EEI6 2 EEI6 1 EEI6 0 EEI5 9 EEI5 8 EEI5 7 EEI5 6 EEI5 5 EEI5 4 EEI5 3 EEI5 2 EEI5 1 EEI5 0 EEI4 9 EEI4 8 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EEI4 7 EEI4 6 EEI4 5 EEI4 4 EEI4 3 EEI4 2 EEI4 1 EEI4 0 EEI3 9 EEI3 8 EEI3 7 EEI3 6 EEI3 5 EEI3 4 EEI3 3 EEI3 2...

Page 134: ...es See Figure 7 7 and Table 7 8 for the DMACERQ definition Figure 7 7 DMA Clear Enable Request DMACERQ Register Table 7 8 DMA Clear Enable Request DMACERQ Field Descriptions 7 3 1 7 DMA Set Enable Error Interrupt DMASEEI The DMASEEI register provides a simple memory mapped mechanism to set a given bit in the DMAEEI H L registers to enable the error interrupt for a given channel The data value on a...

Page 135: ...igure 7 9 and Table 7 10 for the DMACEEI definition Figure 7 9 DMA Clear Enable Error Interrupt DMACEEI Register Table 7 10 DMA Clear Enable Error Interrupt DMACEEI Field Descriptions 7 3 1 9 DMA Clear Interrupt Request DMACINT The DMACINT register provides a simple memory mapped mechanism to clear a given bit in the DMAINT H L registers to disable the interrupt request for a given channel The giv...

Page 136: ... clearing all channel error indicators Reads of this register return all zeroes See Figure 7 11 and Table 7 12 for the DMACERR definition Figure 7 11 DMA Clear Error DMACERR Register Table 7 12 DMA Clear Error DMACERR Field Descriptions 7 3 1 11 DMA Set START Bit DMASSRT The DMASSRT register provides a simple memory mapped mechanism to set the START bit in the TCD of the given channel The data val...

Page 137: ...scriptions 7 3 1 13 DMA Interrupt Request DMAINTH DMAINTL The DMAINT H L registers provide a bit map for the implemented channels 16 32 64 signaling the presence of an interrupt request for each channel DMAINTH supports channels 63 32 while DMAINTL covers channels 31 00 The dma_engine signals the occurrence of a programmed interrupt upon the completion of a data transfer as defined in the transfer...

Page 138: ...the presence of an error for each channel DMAERRH supports channels 63 32 while DMAERRL covers channels 31 00 The dma_engine signals the occurrence of a error condition by setting the appropriate bit in this register The outputs of this register are enabled by the contents of the DMAEEI register then Register address DMA_Offset 0x0020 DMAINTH 0x0024 DMAINTL 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 139: ... writes to the DMAERR a one in any bit position clears the corresponding channel s error status A zero in any bit position has no affect on the corresponding channel s current error status The DMACERR register is provided so the error indicator for a single channel can easily be cleared See Figure 7 15 and Table 7 16 for the DMAERR definition Figure 7 15 DMA Error DMAERRH DMAERRL Registers Registe...

Page 140: ...be temporarily suspended in favor of starting a higher priority channel Once the preempting channel has completed all of its minor loop data transfers the preempted channel is restored and resumes execution After the restored channel completes one read write sequence it is again eligible for preemption If any higher priority channel is requesting service the restored channel will be suspended and ...

Page 141: ... arbitration is enabled These two bits are read only writes are ignored CHPRI 3 0 Channel n Arbitration Priority Channel priority when fixed priority arbitration is enabled DMA Offset TCDn Field 0x1000 32 x n 0x00 Source Address saddr 0x1000 32 x n 0x04 Transfer Attributes smod ssize dmod dsize Signed Source Address Offset soff 0x1000 32 x n 0x08 Inner Minor Byte Count nbytes 0x1000 32 x n 0x0c La...

Page 142: ...Value smod 4 0 Source address modulo 0 Source address modulo feature is disabled non 0 The value defines a specific address bit which is selected to be either the value after saddr soff calculation is performed or the original register value This feature provides the ability to easily implement a circular data queue For data queues requiring power of 2 size bytes the queue should be based at a 0 m...

Page 143: ...d specification of a 16 byte source size in a 64 bit AMBA AHB bus implementation generates a configuration error The attempted specification of a 32 byte burst on platforms that do not support such a transfer type will result in a configuration error dmod 4 0 Destination address modulo See the smod 5 0 definition dsize 2 0 Destination data transfer size See the ssize 2 0 definition soff 15 0 Sourc...

Page 144: ...le operation and cannot be stalled or halted Once the minor count is exhausted the current values of the saddr and daddr are written back into the local memory the major iteration count is decremented and restored to the local memory If the major iteration count is completed additional processing is performed The nbytes value 0x0000_0000 is interpreted as 0x1_0000_0000 thus specifying a 4GB transf...

Page 145: ...igure 7 22 TCDn Word 5 TCDn citer doff Fields Register address DMA_Offset 0x1000 32 x n 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R daddr 31 16 W RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R daddr 15 0 W RESET Unimplemented Name Description Value daddr 31 0 Destination address Memory address pointing to the destination data Register address DMA_Offset 0x1000 32 x n 0x14 31 30 29 28 27 ...

Page 146: ...the inner minor loop is exhausted TCD word 5 bits 30 25 are used to form a 15 bit citer field else After the minor loop is exhausted the dma_engine initiates a channel service request at the channel defined by citer linkch 5 0 by setting that channel s TCD start bit The value contained in citer linkch 5 0 must not exceed the number of implemented channels citer 8 0 Current major iteration count Th...

Page 147: ...ry address for the next transfer control descriptor to be loaded into this channel scatter gather if TCD e_sg 0 then Adjustment value added to the destination address at the completion of the outer major iteration count This value can be applied to restore the destination address to the initial value or adjust the address to reference the next data structure else This address points to the beginni...

Page 148: ... e_link 0 then No channel to channel linking or chaining is performed after the inner minor loop is exhausted TCD word 5 bits 30 25 are used to form a 15 bit biter field else After the minor loop is exhausted the dma_engine initiates a channel service request at the channel defined by biter linkch 5 0 by setting that channel s TCD start bit The value contained in biter linkch 5 0 must not exceed t...

Page 149: ...es 00 No dma_engine stalls 01 Dynamic priority elevation 10 dma_engine stalls for 4 cycles after each r w 11 dma_engine stalls for 8 cycles after each r w major linkch 5 0 Link channel number if TCD major e_link 0 then No channel to channel linking or chaining is performed after the outer major loop counter is exhausted else After the major loop counter is exhausted the dma_engine initiates a chan...

Page 150: ...o zero when written to while the TCD done bit is set 0 The current channel s TCD is normal format 1 The current channel s TCD specifies a scatter gather format The dlast_sga field provides a memory pointer to the next TCD to be loaded into this channel after the outer major loop completes its execution d_req Disable request If this flag is set the DMA hardware automatically clears the correspondin...

Page 151: ...annel is activated the contents of its transfer control descriptor is read from the local memory and loaded into the registers of the other addr_path channel_ x y Once the inner minor loop completes execution the addr_path hardware writes the new values for the TCDn saddr daddr citer back into the local memory If the major iteration count is exhausted additional processing is performed including t...

Page 152: ...rom both the dma_engine as well as references from the IPS bus As noted earlier in the event of simultaneous accesses the dma_engine is given priority and the IPS transaction is stalled The hooks to a BIST controller for the local TCD memory are included in this module memory array The TCD is implemented using a single ported synchronous compiled RAM memory array 7 4 2 DMA Basic Data Flow The basi...

Page 153: ...e through the required source reads and destination writes to perform the actual data movement The source reads are initiated and the fetched data is temporarily stored in the data_path module until it is gated onto the AMBA AHB bus during the j j 1 n 1 SRAM Transfer Control Descriptor TCD dma_engine addr_path data_path DMA IPS Bus AMBA Bus ipd_req n 1 0 dma_ipi_int n 1 0 0 c o n t r o l pmodel_ch...

Page 154: ...nt the addr_path logic performs the required updates to certain fields in the channel s TCD e g saddr daddr citer If the outer major iteration count is exhausted then there are additional operations which are performed These include the final address adjustments and reloading of the biter field into the citer Additionally assertion of an optional interrupt request occurs at this time as does a pos...

Page 155: ...f the source and destination address spaces In a second context where device paced movement of single data values to from peripherals is dominant a measure of the requests which can be serviced in a fixed time is a more interesting metric In this environment the speed of the source and destination address spaces remains important but the microarchitecture of the DMA also factors significantly into...

Page 156: ...ipd_req n is registered locally in the DMA module and qualified TCD start bit initiated requests start at this point with the registering of the IPS write to TCD word7 Cycle 3 Channel arbitration begins Cycle 4 Channel arbitration completes The transfer control descriptor local memory read is initiated Cycle 5 6 The first two parts of the activated channel s TCD is read from the local memory The m...

Page 157: ...o Cycle 4 for the first channel s service request Assuming zero wait states on the AHB system bus DMA requests can be processed every 9 cycles Assuming an average of the access times associated with IPS to SRAM 4 cycles and SRAM to IPS 5 cycles DMA requests can be processed every 11 5 cycles 4 4 5 2 3 This is the time from Cycle 4 to Cycle 5 The resulting peak request rate as a function of the pla...

Page 158: ... signal request Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the ipd_req signals For the peak request rate calculations above the arbitration and request registering is absorbed in or overlap the previous executing channel NOTE When channel linking or scatter gather is enabled a two cycle delay is imposed on ...

Page 159: ...oup or Channel Priority Errors the channel number causing the error is recorded in the DMAES register If the error source is not removed before the next activation of the problem channel the error will be detected and recorded again The sequence listed below is correct For item 2 the dma_ipd_ack done lines will assert only if the selected channel is requesting service via the ipd_req signal I thin...

Page 160: ...hest group number with an service request and rotating through to the lowest group number containing a service request Once the channel request is serviced the group round robin algorithm will select the highest pending request from the next group in the round robin sequence Servicing continues round robin always servicing the highest priority channel in the next group in the sequence or just skip...

Page 161: ...enario could cause the same bandwidth consumption problem as indicated in Section 7 5 3 1 Fixed group arbitration fixed channel arbitration but all the channels in the highest priority group will get serviced Service latency will be short on the highest priority group but could potentially get very much longer and longer as the group priority decreases 7 5 4 DMA Transfer 7 5 4 1 Single request To ...

Page 162: ...yte 0x1005 read_byte 0x1006 read_byte 0x1007 d write_word 0x2004 second iteration of the minor loop e read_byte 0x1008 read_byte 0x1009 read_byte 0x100a read_byte 0x100b f write_word 0x2008 third iteration of the minor loop g read_byte 0x100c read_byte 0x100d read_byte 0x100e read_byte 0x100f h write_word 0x200c last iteration of the minor loop major loop complete 6 dma_engine writes TCD saddr 0x1...

Page 163: ...minor loop g read_byte 0x100c read_byte 0x100d read_byte 0x100e read_byte 0x100f h write_word 0x200c last iteration of the minor loop 6 dma_engine writes TCD saddr 0x1010 TCD daddr 0x2010 TCD citer 1 7 dma_engine writes TCD active 0 8 The channel retires one iteration of the major loop The DMA goes idle or services next channel 9 Second hardware ipd_req requests channel service 10 The channel is s...

Page 164: ...TCD done 0 channel is executing 3 TCD start 0 TCD active 0 TCD done 0 channel has completed the minor loop and is idle or 4 TCD start 0 TCD active 0 TCD done 1 channel has completed the major loop and is idle The best method to test for minor loop completion when using hardware initiated service requests is to read the TCD citer field and test for a change The hardware request and ackowledge hands...

Page 165: ...TCD map indicates a higher priority channel is actively preempting a lower priority channel The worst case latency when switching to a preempt channel is the summation of arbitration latency 2 cycles bandwidth control stalls if enabled the time to execute two read write sequences including AHB bus holds a system dependency driven by the slave devices or the crossbar 7 5 6 Channel Linking Channel l...

Page 166: ...ck to fixed arbitration mode 2 Disable all the channels within a group then change the channel priorities within that group only then enable the appropriate channels The following two options are available for dynamically changing group priority levels 1 Switch to round robin group arbitration mode change the group priorities then switch back to fixed arbitration mode 2 Disable ALL channels change...

Page 167: ... s TCD word7 once that channel s TCD done bit is set indicating the major loop is complete NOTE The user must clear the TCD done bit before writing the TCD major e_link or TCD e_sg bits The TCD done bit is cleared automatically by the dma_engine once a channel begins execution 7 5 8 Hardware Request Release Timing This section provides a timing diagram for deasserting the ipd_req hardware request ...

Page 168: ...MPC563XM Reference Manual Rev 1 168 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 169: ...er ports e200z335 core complex Instruction port e200z335 core complex Load Store port eDMA Four slave ports Flash memory SRAM Peripheral bridge B eTPU SIU DSPI eSCI FlexCAN eQADC BAM Calibration bus 32 bit internal address 64 bit internal data paths 64 bit for instruction fetch AXBS halt mode is not supported on this device The functionality associated with axbs_halt_request is not implemented as ...

Page 170: ...truction 0 Master 1 eDMA 2 Master 4 e200z335 core Load Store 0 e200z335 core Nexus 1 Slave 0 Flash memory Slave 1 Calibration bus Slave 3 SRAM Slave 7 Peripheral bridge Table 8 2 Crossbar Register Addresses Slave Port Addresses Master Priority Register General Purpose Control Register Slave 0 internal flash memory 0xFFF0_4000 0xFFF0_4010 Slave 1 calibration bus interface 0xFFF0_4100 0xFFF0_4110 Sl...

Page 171: ...tions between master ports and slave ports The XBAR supports a 32 bit address bus width and almost any data bus width at all master and slave ports Only a single data bus width is supported via a synthesis parameter throughout the design thus all master and slave ports have the same data bus width NOTE The 8 x 8 configuration is the generic configuration Please reference your project specific spec...

Page 172: ...r s Slv hready Slv hresp Slave 7 read data Slv addr Slv cntrl Slv wdata IP cntrl IP wdata IP rdata IP term halt request halt grant Master Port 7 Mstr addr Mstr control Master 7 write data IP rdata Mstr Port request Mstr Port addr Mstr read data Mstr hready Mstr hresp Slv port hready s Slv port hresp s Slv port hrdata s General Purpose Logic IP cntrl IP wdata IP rdata IP term IP term s IP wdata s I...

Page 173: ...er and grant it ownership of the slave port All other masters requesting that slave port will stalled until the higher priority master completes its transactions 8 2 3 Limitations The XBAR routes bus transactions initiated on the master ports to the appropriate slave ports There is no provision included to route transactions initiated on the slave ports to other slave ports or to master ports Simp...

Page 174: ...ave port for its next access The master could also lose control of the slave port if another higher priority master makes a request to the slave port however if the master is running a locked or fixed length burst transfer it will retain control of the slave port until that transfer is completed Based on the AULB bit in the MGPCR Master General Purpose Control Register the master will either retai...

Page 175: ...ister for Slave port 2 0x210 SGPCR2 General Purpose Control Register for Slave port 2 0x214 ASGPCR2 Alternate General Purpose Control Register for Slave port 2 0x300 MPR3 Master Priority Register for Slave port 3 0x304 AMPR3 Alternate Master Priority Register for Slave port 3 0x310 SGPCR3 General Purpose Control Register for Slave port 3 0x314 ASGPCR3 Alternate General Purpose Control Register for...

Page 176: ...e 1 to Clear bit Self Clear Bit 0 N A bit w1c bit Table 8 4 XBAR Register Summary Name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPRn BASE 0x000 n 0x100 R 0 MSTR_7 0 MSTR_6 0 MSTR_5 0 MSTR_4 W R 0 MSTR_3 0 MSTR_2 0 MSTR_1 0 MSTR_0 W AMPRn BASE 0x004 n 0x100 R 0 MSTR_7 0 MSTR_6 0 MSTR_5 0 MSTR_4 W R 0 MSTR_3 0 MSTR_2 0 MSTR_1 0 MSTR_0 W SGPCRn BASE 0x010 ...

Page 177: ... 5 Register Terms Term Description Grey bit Unimplemented bit always reads as zero writing has no effect Access S Supervisor mode only Supervisor or user mode Type r Read only writing to this bit has no effect w Write only rw Standard read write bit Only software can change a bit s value other than a hardware reset rwm A read write bit that may be modified by hardware in some fashion other than re...

Page 178: ...d by hardware reset The reset value is 111 000This master has the highest priority when accessing the slave port 111This master has the lowest priority when accessing the slave port Bit 27 Master Priority Register Reserved This bit is reserved for future expansion It is read as zero and should be written with zero for upward compatibility NA MSTR_6 Bits 26 24 Master 6 Priority These bits set the a...

Page 179: ...000This master has the highest priority when accessing the slave port 111This master has the lowest priority when accessing the slave port Bit 11 Master Priority Register Reserved This bit is reserved for future expansion It is read as zero and should be written with zero for upward compatibility NA MSTR_2 Bits 10 8 Master 2 Priority These bits set the arbitration priority for master port 2 on the...

Page 180: ...esses Once the RO Read Only bit has been set in the General Purpose Control Register the Alternate Master Priority Register can only be read from attempts to write to it will have no effect on the AMPR and result in an error response Additionally no two available master ports may be programmed with the same priority level Attempts to program two or more available masters with the same priority lev...

Page 181: ...is requesting an access The low power park feature can result in an overall power savings if a the slave port is not saturated however it will force an extra clock of latency whenever any master tries to access it when it is not in use because it will not be parked on any master The PARK bits determine which master the slave will park on when no master is making an active request and the max_halt_...

Page 182: ...eset The reset value is 0 0 The mX_high_priority input is disabled on this slave port 1 The mX_high_priority input is enabled on this slave port Bits 15 10 Slave General Purpose Control Register Reserved These bits are reserved for future expansion They are read as zero and should be written with zero for upward compatibility NA ARB Bits 9 8 Arbitration Mode These bits are used to select the arbit...

Page 183: ...ASGPCR does not contain a RO Read Only bit The RO bit in the SGPCR has control over the ASGPCR s ability to be written PARK Bits 2 0 PARK These bits are used to determine which master port this slave port parks on when no masters are actively making requests and the PCTL bits are set to 00 These bits are initialized by hardware reset The reset value is 000 000Park on Master Port 0 001Park on Maste...

Page 184: ... complete uninterrupted or whether they can be broken by requests from higher priority masters The AULB Arbitrate on Undefined Length Bursts bit field determines whether and when or not the XBAR will arbitrate away the slave port the master owns when the master is performing undefined length burst accesses If the user has configured the XBAR to have less than 8 master ports only the registers asso...

Page 185: ...ection describes in more detail the functionality of the XBAR 8 4 1 Arbitration The XBAR supports two arbitration schemes a simple fixed priority comparison algorithm and a simple round robin fairness algorithm The arbitration scheme is independently programmable for each slave port Table 8 8 Master General Purpose Control Register Descriptions Name Description Setting Bits 31 3 Master General Pur...

Page 186: ...on Note that fixed length burst accesses will not be affected by the AULB bits All fixed length burst accesses will lock out arbitration until the last beat of the fixed length burst 8 4 1 2 Fixed Priority Operation When operating in fixed priority mode each master is assigned a unique priority level in the MPR Master Priority Register and AMPR Alternate Master Priority Register If two masters bot...

Page 187: ... occur to the next master in line after one cycle of arbitration If the slave port is put into low power park mode the round robin pointer will be reset to point at master port 0 giving it the highest priority Each master port has an mX_high_priority input which can be enabled by writing the correct data to the SGPCR or ASGPCR If a master s mX_high_priority input is enabled for a slave port progra...

Page 188: ...e a mux and a small state machine The first decoder is used to decode the mX_hsel_slv and control signals coming directly from the master telling the state machine where the master s next access will be and if it is in fact a legal access The second decoder gets its input from the capture unit so it may be looking directly at the signals coming from the master or it may be looking at captured sign...

Page 189: ...rl Next_slave_port 7 0 Illegal_access Capture Unit Addr Cntrl Async Flopped_sel Addr Cntrl Decoder Addr Cntrl Slave_port_rqst 7 0 Request_enable State Machine Next_slave_port 7 0 Illegal_access Request_enable Async Flopped_sel Rdata_sel Slv_hready 7 0 Slv_hresp 7 0 Hready_in Hready_out Slv_is_mine 7 0 Hresp Mux Hrdata Slv_hrdata 7 0 Sel Registers Read_sel Write_sel Xfr_wait Xfr_error Wdata Rdata C...

Page 190: ... Port Registers The registers in the master port are only those registers associated with this particular master port The read and write interface for the registers is a quasi IP bus interface It is not a full IP bus interface at this level because not all the IP bus signals are routed this deep in the design There is a register control block at the same level of the master port and slave port ins...

Page 191: ... when possible any bubbles that would get inserted into the access due to switching slave ports The state machine will not allow the master to request access to another slave port until the current access being made is terminated This prevents a single master from owning two slave ports at the same time the slave port it is currently accessing and the slave port it wishes to access next The state ...

Page 192: ... Slave Port Block Diagram 8 4 4 2 Slave Port Muxes The block diagram Figure 8 9 shows only one block for all the muxes In reality that block instantiates many 8 to 1 muxes one for each master to slave signal in fact All the muxes are designed in an AND OR fashion so that if no master is selected the output of the muxes will be zero This is an important feature for low power park mode Registers Rea...

Page 193: ...his deep in the design The register outputs are connected directly to the slave state machine with the sX_ampr_sel input determining which priority register values halt priority value arbitration algorithm and parking control bits are passed to the state machine The registers can be read from an unlimited number of times The registers can only be written to as long as the RO bit is written to 0 in...

Page 194: ...highest priority and it gives up the slave port by either running and IDLE cycle to the slave port or running a valid access to a location other than the slave port If the current master loses control of the slave port because a higher priority master takes it away the slave port will not incur any wasted cycles The current master will get its current cycle terminated by the slave port at the same...

Page 195: ...s requesting the bus then IDLE cycles will be run by the XBAR but no bandwidth will truly be lost since no master is making a request Figure 8 11 illustrates the effect of a higher priority master giving up control of the bus Figure 8 11 High to low priority mastership change When the slave port is programmed for round robin mode of arbitration then the slave port will switch masters any time ther...

Page 196: ...park mode It will not recognize any master as being in control of it and it will not select any master s signals to pass through to the slave bus In this case all slave bus activity will effectively halt because all slave bus signals being driven from the XBAR will be 0 This of course can save quite a bit of power if the slave port will not be in use for some time The down side is that when a mast...

Page 197: ...Figure 8 13 illustrates parking on a specific master Figure 8 13 Parking on a specific master Figure 8 14 illustrates parking on the last master Note that in cycle 6 simultaneous requests are made by master 2 and master 4 Although master 2 has higher priority the slave bus is parked on master 4 so master 4 s access will be taken first The slave port parks on master 2 once it has given control to m...

Page 198: ... until no masters are actively making requests before moving to halt mode Regardless of the state of the HLP bit once the slave port has gone into halt mode as a result of max_halt_request being asserted it will remain in halt mode until max_halt_request is negated regardless of the priority level of any masters that may make requests In halt mode no master is selected to own the slave port so all...

Page 199: ...lave port to which the access decodes is either currently servicing the master or is parked on the master In this case the XBAR will be completely transparent and the master s access will be immediately seen on the slave bus and no arbitration delays will be incurred 8 6 2 4 Stalled Accesses A master access will be stalled if the hsel input of the XBAR is asserted and the transfer type is non IDLE...

Page 200: ... zero wait state accesses while a lower priority master is stalled waiting for control of the slave port When the higher priority master either leaves the slave port or runs an IDLE cycle to the slave port the XBAR will take control of the slave bus and run a single IDLE cycle before giving the slave port to the lower priority master that was waiting for control of the slave port The only other ti...

Page 201: ...rals Supports 32 bit IPS peripherals byte halfword and word reads and write are supported to each Supports a pair of IPS accesses for 64 bit fetches 9 2 PBRIDGE Modes of Operation The PBRIDGE has only one operating mode 9 3 PBRIDGE Block Diagram The PBRIDGE is the interface between the system bus interface and on chip peripherals as shown in Figure 9 1 Figure 9 1 PBRIDGE Interface 9 4 PBRIDGE Sign...

Page 202: ...ible with the PBRIDGE when the requested access size is 32 bits or smaller and is not misaligned across a 32 bit boundary If the requested instruction access size is 64 bits then a minimum of three clocks are required to complete the access Misaligned read accesses are not supported 64 bit data reads not instruction are not supported 9 5 2 Write Cycles Three clock write accesses are possible with ...

Page 203: ...through the Standard Product Platform to on chip memories e g flash and SRAM where the processor and platform operate at the same frequency For these applications the 2 stage pipeline AMBA AHB system bus is effectively mapped directly into stages of the processor s pipeline and zero wait state responses for most memory accesses is critical for providing an acceptable level of system performance 10...

Page 204: ...ram Figure 10 1 shows a block diagram of the PFLASH_C90FL Figure 10 1 PFLASH_C90FL Block Diagram 10 2 5 Signal Description The PFLASH_C90FL has no external signals 10 2 6 Functional Description The PFLASH_C90FL generates read and write enables the flash array address write size and write data as inputs to the flash array controller The PFLASH_C90FL captures read data from the flash array interface...

Page 205: ...ections for both read and write cycles from masters It allows restriction of read and write requests on a per master basis The PFLASH_C90FL also supports software configurable access protections Detection of a protection violation results in an error response from the PFlash Memory Controller to the system bus 10 2 6 3 Read Cycles Buffer miss Read data is normally stored in the least recently upda...

Page 206: ... least recently used buffer Buffers can be in one of six states listed here in prioritized order 1 Invalid the buffer contains no valid data 2 Used the buffer contains valid data which has been provided to satisfy a burst type read 3 Valid the buffer contains valid data which has been provided to satisfy a single type read 4 Prefetched the buffer contains valid data which has been prefetched to sa...

Page 207: ...eserved for data accesses 10 2 6 10 Buffer Invalidation The line read buffers can be invalidated under hardware and software control 10 2 6 11 Wait state Emulation Emulation of other memory array timings are supported by the PFlash Memory Controller This functionality can be useful to maintain the access timing for blocks of memory which were used to overlay Flash blocks for the purpose of system ...

Page 208: ... provide for timing emulation of alternate memory types The PFlash Memory Controller address scheme is shown in Figure 10 2 Figure 10 2 PFlash Memory Controller Address Scheme Write accesses must be either word or doubleword in size and must be aligned Unaligned writes and byte or halfword writes result in an error termination on the system bus side and no flash array write is initiated Table 10 2...

Page 209: ...lash Shadow Row Serial Passcode Low Word 0xCAFE_BEEF FLASH_BASE 0xFF_BDE0 Flash Shadow Row Censorship Control word 0x55AA_55AA FLASH_BASE 0xFF_BDE4 For General Use FLASH_BASE 0xFF_BDE8 Flash Shadow Row LBL reset configuration 0x0100_03FF FLASH_BASE 0xFF_BDEC For General Use FLASH_BASE 0xFF_BDF0 Flash Shadow Row HBL reset configuration 0x0000_003F FLASH_BASE 0xFF_BDF4 For General Use FLASH_BASE 0xF...

Page 210: ... This field is used to control the number of cycles between pipelined access requests This field must be set to a value corresponding to the operating frequency of the PFLASH_C90FL The required settings are documented in Table 10 5 This field is set to 111 by hardware reset 000 001 010 110 111 Accesses may be pipelined back to back Accesses require one additional hold cycle Accesses require two ad...

Page 211: ... read access This field is cleared by hardware reset 0 1 No prefetching is triggered by an instruction read access Prefetching may be triggered by any instruction read access PFLIM PFLASH Prefetch Limit This field controls the prefetch algorithm used by the PFLASH prefetch controller This field defines a limit on the maximum number of sequential prefetches which will be attempted between buffer mi...

Page 212: ...This APC RWSC WWSC combination requires setting the flash MCR register bit PRD 1 FLASH_REGS_BASE 0x20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R M3AP M2AP M1AP M0AP W RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Unimplemented or Reserved Table 10 6 PFlash Access Protection Register PFAPR Table 10 7 PFAPR Field Descript...

Page 213: ...e four line buffers Table 10 9 Crossbar Master ID Master ID Master Name 0 Core 1 Nexus 2 eDMA 3 EBI FLASH_REGS_BASE 0x24 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R LBCFG W RESET Note1 1 The reset value is read from address 0x7E00 of the Shadow Block of the Flash array 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R W RESET Unimplemented or Reserved Table 10 10 PFlash Configuration Register 2 PFCR2 ...

Page 214: ...rfaces the system bus on this device to the C90FL memory block The PFlash BIU is described in Section 10 2 Platform Flash PFlash Memory Controller The base address for the flash bus and flash registers is 0x03F8_8000 There are three address spaces Low Address Space 256 Kbytes Table 10 11 PFCR2 Field Descriptions Field Description Settings LBCFG Line Buffer Configuration This field controls the con...

Page 215: ...s in the buffers Hardware and software configurable read and write access protections on a per master basis Interface to the flash array controller is pipelined with a depth of 1 allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs Configurable access timing allowing use in a wide range of system frequencies Multiple mapping support and mapping based...

Page 216: ... volatile shadow block Independent program erase of the shadow block 10 3 3 C90FL Modes of Operation 10 3 3 1 C90FL User Mode User mode is the default operating mode of the C90FL module In this mode it is possible to read and write program and erase the C90FL module 10 3 3 2 Stop Mode In Stop mode all DC current sources in the C90FL are disabled 10 3 4 C90FL Block Diagram Figure 10 4 shows a block...

Page 217: ... reads to be done with higher performance This can create a Data Coherency issue that must be handled with software Data Coherency can be an issue after a program or erase operation as well as shadow row operations In C90FL user mode registers can be written Array can be written to do interlock writes Reads attempted to invalid locations will result in indeterminate data Invalid locations occur wh...

Page 218: ...ten through register writes and can be read through register reads 10 3 5 6 C90FL Program Suspend Resume A program suspend operation is initiated by setting the PSUS bit in the MCR Once suspended the Flash can be read Reads to the block s being programmed erased return indeterminate data The program operation is resumed by clearing the PSUS bit When the operation resumes the C90FL continues the pr...

Page 219: ...t is the highest priority operation for the C90FL and terminates all other operations The C90FL uses reset to initialize register and status bits to their default reset values If the C90FL is executing a program or erase operation and a reset is issued the operation will be aborted and the C90FL will disable the high voltage logic without damage to the high voltage circuits Reset aborts all operat...

Page 220: ...ASH_BASE 0xFF_CDFC For General Use FLASH_BASE 0xFF_CE00 Flash Shadow Block PFCR2 reset configuration FLASH_BASE 0xFF_CE04 FLASH_BASE 0xFF_FFFF Flash Shadow Block For General Use 1 For Read while Write operations shadow row behaves as if it is in all partitions Table 10 13 Register Memory Map Address Use FLASH_REGS_BASE 0x0 MCR Register MCR FLASH_REGS_BASE 0x4 LML Register LML FLASH_REGS_BASE 0x8 H...

Page 221: ...000 128 KB only LAS option for this size is LAS 2 and consists of two 16 KB and two 48 KB blocks 128 KB of LAS available and no MAS or HAS available 001 256 KB only LAS option for this size is LAS 1 and LAS 2 no MAS or HAS available 010 512 KB Any LAS or MAS option is available no HAS available 011 1 0 MB 256 KB of LAS 256 KB of MAS and 512 KB of HAS 100 1 5 MB 256 KB of LAS 256 KB of MAS and 1 MB...

Page 222: ...t all previous reads from the last reset or clearing of SBC did not require a correction Since this bit is an error flag it must be cleared to a 0 by writing a 1 to the register location A write of 0 has no effect 0 Reads are occurring without corrections 1 A Single Bit Correction occurred during a previous read 19 Reserved reset to 0 20 PEAS Program Erase Access Space PEAS is used to indicate whi...

Page 223: ...m sequence PGM can be set only under one of the following conditions User mode read ERS is low and UTE is low Erase suspend ERS and ESUS are 1 with EHV low PGM can be cleared by the user only when PSUS and EHV are low and DONE is high PGM is cleared on reset 0 Flash is not executing a program sequence 1 Flash is executing a program sequence Note In an erase suspended program programming Flash loca...

Page 224: ...e is suspended 31 EHV Enable High Voltage The EHV bit enables the flash module for a high voltage program erase operation EHV is cleared on reset EHV must be set after an interlock write to start a program erase sequence EHV may be set initiating a program erase after an interlock under one of the following conditions Erase ERS 1 ESUS 0 Program ERS 0 ESUS 0 PGM 1 PSUS 0 Erase suspended program ERS...

Page 225: ...is unaffected 10 3 6 2 Low Mid Address Space Block Locking Register The Low Mid Address Block Locking Register LML provides a means to protect blocks from being modified These bits along with bits in the Secondary LLOCK SLL determine if the block is locked from program or erase An OR of LML and SLL determine the final lock status NOTE A reset value of 1 in Table 10 17 indicates that the reset valu...

Page 226: ...urs For LME the password 0xA1A1_1111 must be written to the LML register 0 Low Mid Address Locks are disabled and can not be modified 1 Low Mid Address Locks are enabled to be written 1 10 Reserved reset to 0 11 SLOCK Shadow Lock This bit is used to lock the shadow block from programs and erases A value of 1 in the SLOCK register signifies that the shadow block is locked for program and erase A va...

Page 227: ...d operation Likewise the lock register is not writable if a high voltage operation is suspended MLOCK is also not writeable during UTest operations when AIE is high Upon reset information from the shadow block is loaded into the block registers The LOCK bits may be written as a register Reset causes the bits to go back to their shadow block value The default value of the LOCK bits assuming erased ...

Page 228: ... 0 0 0 0 0 0 HLOCK W RESET 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Unimplemented or Reserved Table 10 19 HBL Register Table 10 20 HBL Field Descriptions Field Description 0 HBE High Address Lock Enable This bit is used to enable the Lock registers HLOCK to be set or cleared by register writes This bit is a status bit only and may not be written or cleared and the reset value is 0 The method to set this bi...

Page 229: ...is used to enable the Lock registers SSLOCK SMLOCK and SLLOCK to be set or cleared by register writes This bit is a status bit only and may not be written or cleared and the reset value is 0 The method to set this bit is to provide a password and if the password matches the SLE bit is set to reflect the status of enabled and is enabled until a reset operation occurs For SLE the password 0xC3C3_333...

Page 230: ... Reserved reset to 0 22 31 SLLOCK 9 0 Secondary Low Address Block Lock This bit is an alternative method that may be used to lock the Low Address Space blocks from programs and erases SLLOCK has the same description as LLOCK SLLOCK is not writable unless SLE is high Offset 0x0010 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEL W RESET 0 0 0 0 0 0 0 0...

Page 231: ...tage operation is suspended MSEL is also not writeable during UTest operations when AIE is high In the event that blocks are not present due to configuration or total memory size the corresponding select bits default to unselected and are not writable The reset value is always 0 and register writes have no effect 16 21 Reserved reset to 0 22 31 LSEL 9 0 Low Address Space Block Select A value of 1 ...

Page 232: ...scriptions fully define the ADR register Table 10 27 Offset 0x0014 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 HSEL W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 10 25 HBS Register Table 10 26 HBS Field Descriptio...

Page 233: ...address in the event of ECC event error MCR EER set single bit correction MCR SBC set as well as providing the address of a failure that may have occurred in a state machine operation MCR PEG cleared ECC event errors take priority over single bit corrections which take priority over state machine errors This is especially valuable in the event of a RWW operation where the read senses an ECC error ...

Page 234: ...quest require one additional hold cycle 63 MHz Operating Frequency 125 MHz 010 Access request require two additional hold cycles 125 MHz Operating Frequency 133 MHz 011 Access request require three additional hold cycles Not needed for spec frequency range of c90fl 100 Access request require four additional hold cycles Not needed for spec frequency range of c90fl 101 Access request require five ad...

Page 235: ...c90fl NOTE For Address Pipelined Control and Read Wait State Control it should be noted that pipelining can only be utilized at 53 MHz to 63 MHz or 90 MHz to 125 MHz Thus it is possible to achieve better overall performance due to pipelining at 125 MHz than executing reads non pipelined by design at 133 MHz WARNING For frequencies that correspond to access times approaching the c90fl read access t...

Page 236: ...shadow block causes the reset value to be 1 BIU2 register functions are shown in Table 10 34 Offset 0x0020 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BIU1 W writability is SOC specified Reset reset is SOC specified Table 10 31 BIU1 Register Table 10 32 BIU1 Field Descriptions Field Description 0 31 BIU1 31 0 BIU1 Generic Registers...

Page 237: ...The Bus Interface Unit 4 Register BIU4 provides a means for BIU specific information or BIU configuration information to be stored These registers are loaded with NVM information from the shadow block during reset 10 3 6 12 1 BIU4 Register The following field and bit descriptions fully define the BIU4 register Table 10 37 NOTE 1 indicates that the reset value of these registers is determined by Fl...

Page 238: ...40 Offset 0x002c Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BIU4 W writability is SOC specified Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 10 37 BIU4 Register Table 10 38 BIU4 Field Descriptions Field Description 0 31 BIU4 31 0 BIU4 Generic Registers The BIU generic registers are reset based on the...

Page 239: ...R is calculated by taking the previous MISR value and then exclusive ORing the new data In addition the most significant bit in this case it is MISR 144 is then exclusive ORed into input of MISR 6 MISR 5 MISR 1 and MISR 0 The result of the exclusive OR is shifted left on each read The MISR register is used in Array Integrity operations If during address sequencing reads extend into an invalid addr...

Page 240: ... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MISR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 43 UM2 Register Table 10 44 UM2 Field Descriptions Field Description 0 31 MISR 95 64 See the description of the MISR field in Table 10 40 Offset 0x0054 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ...

Page 241: ...er read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MISR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10 47 UM4 Register Table 10 48 UM4 Field Descriptions Field Description 0 14 Reserved reset to 0 15 31 MISR 144 12 8 See the description of the MISR in Table 10 40 ...

Page 242: ...MPC563XM Reference Manual Rev 1 242 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 243: ...al for program and data storage for single chip applications allowing for field reprogramming without requiring external programming voltage sources The module is a solid state silicon memory device consisting of blocks of single transistor storage elements The device Flash contains a Flash bus interface unit FBIU and a Flash memory array The Flash BIU interfaces the system bus to a dedicated Flas...

Page 244: ... support RWW within its sectors But RWW read while write is supported between partitions 11 4 Features 11 4 1 FBIU features The following list summarizes the key features of the FBIU The FBIU system bus interface supports a 32 bit data bus All byte halfword and word reads are supported Only aligned word writes are supported The Flash array interface supports a 128 bit read data bus and a 32 bit wr...

Page 245: ...he actual Flash array is multiply mapped within this space 11 6 1 Flash Memory Map Table 11 1 shows the Flash array memory map and how it is mapped using byte addressing Base addresses for the device are the following Shadow base address 0x0020_0000 Array base address 0x0000_0000 Test Flash base address 0x0040_0000 Control registers base address 0xC3F8_8000 Table 11 1 Module Flash Array Memory Map...

Page 246: ...tio n Array Base 0x0000_0000 Low Address Space LAS L0 16 Kbyte 0 Array Base 0x0000_4000 L1a 16 Kbyte Array Base 0x0000_8000 L1b 32 Kbyte Array Base 0x0001_0000 L2a 32 Kbyte Array Base 0x0001_8000 L2b 16 Kbyte Array Base 0x0001_C000 L3 16 Kbyte Array Base 0x0002_0000 L4 64 Kbyte Array Base 0x0003_0000 L5 64 Kbyte Array Base 0x0004_0000 Mid Address Space MAS M0 128 Kbyte Array Base 0x0006_0000 M1 12...

Page 247: ... byte 1 MPC5634M and MPC5633M only 2 MPC5634M only Table 11 3 Module Register Memory Map Byte Address Register Name Register Description Size bits Register Base 0x00 CFLASH_MCR Module configuration register 32 Register Base 0x04 CFLASH_LMLR Low mid address space block locking register 32 Register Base 0x08 Reserved 32 Register Base 0x0C CFLASH_SLMLR Secondary low mid address space block locking re...

Page 248: ...r Base 0x44 CFLASH_UT2 User Test 2 register 32 Register Base 0x48 CFLASH_UMISR0 User Multiple Input Signature Register 0 32 Register Base 0x4C CFLASH_UMISR1 User Multiple Input Signature Register 1 32 Register Base 0x50 CFLASH_UMISR2 User Multiple Input Signature Register 2 32 Register Base 0x54 CFLASH_UMISR3 User Multiple Input Signature Register 3 32 Register Base 0x58 CFLASH_UMISR4 User Multipl...

Page 249: ...rved 15 MAS Mid address space size Corresponds to the configuration of the mid address space MAS is read only 0 Two 128 KB blocks are available 16 EER ECC event error Provides information on previous reads if a double bit detection occurred the EER bit is set to 1 This bit must then be cleared or a reset must occur before this bit returns to a 0 state This bit cannot be set by the application In t...

Page 250: ...ing the sequence failed PEG is set to 1 when the Flash Module is reset unless a Flash initialization error has been detected The value of PEG is valid only when PGM 1 and or ERS 1 and after DONE transitions from 0 to 1 due to an abort or the completion of a Program Erase operation PEG is valid until PGM ERS makes a 1 to 0 transition or EHV makes a 0 to 1 transition The value in PEG is not valid af...

Page 251: ...ing a program erase after an interlock write under one of the following conditions Erase ERS 1 ESUS 0 Program ERS 0 ESUS 0 PGM 1 PSUS 0 Erase suspended program ERS 1 ESUS 1 PGM 1 PSUS 0 If a program operation is to be initiated while an erase is suspended the user must clear EHV while in erase suspend before setting PGM In normal operation a 1 to 0 transition of EHV with DONE high PSUS and ESUS lo...

Page 252: ...ttempts to write two or more MCR bits simultaneously then only the bit with the highest priority level is written Setting two bits with the same priority level is prevented by existing write locks and does not put the Flash in an illegal state For example setting CFLASH_MCR STOP and CFLASH_MCR PGM simultaneously results in only CFLASH_MCR STOP being set Attempting to clear CFLASH_MCR EHV while set...

Page 253: ...lock enable Enables the locking register fields SLOCK MLOCK and LLOCK to be set or cleared by register writes This bit is a status bit only and cannot be written or cleared and the reset value is 0 The method to set this bit is to write a password and if the password matches the LME bit is set to reflect the status of enabled and is enabled until a reset operation occurs For LME the password 0xA1A...

Page 254: ... shadow row value The default value of the LOCK bits assuming erased fuses would be locked In the event that blocks are not present due to configuration or total memory size the LOCK bits default to locked and are not writable The reset valueis always 1 independent of the shadow row and register writes have no effect MLOCK is not writable unless LME is high 16 25 Reserved 26 31 LLOCK 5 0 Low addre...

Page 255: ...g Register CFLASH_LMLR SSLOCK is not writable unless SLE is high 12 13 Reserved 14 15 SMLOCK 1 0 Secondary mid address block lock Alternative method to lock the mid address space blocks from programs and erases SMLOCK has the same description as MLOCK in Section 11 6 2 2 Low Mid Address Space Block Locking Register CFLASH_LMLR SMLOCK is not writable unless SLE is set In the event that blocks are n...

Page 256: ...write as part of the erase sequence The select register is not writable after an interlock write is completed or if a high voltage operation is suspended In the event that blocks are not present due to configuration or total memory size the corresponding SELECT bits default to unselected and are not writable The reset value is always 0 and register writes have no effect A description of how blocks...

Page 257: ... PEG cleared The Address Register provides also the first address at which a ECC single error correction occurs MCR EDC set if the SoC is configured to show this feature The ECC double error detection takes the highest priority followed by the RWW error the FPEC error and the ECC single error correction When accessed ADR will provide the address related to the first event occurred with the highest...

Page 258: ...ncies require non zero settings for this field for proper Flash operation This field is set to 0b00010 by hardware reset 00000 Accesses may be initiated on consecutive back to back cycles 00001 Access requests require one additional hold cycle 00010 Access requests require two additional hold cycles 11110 Access requests require 30 additional hold cycles 11111 Access requests require 31 additional...

Page 259: ...ication interrupt 110 Generate a bus stall for a read while write erase enable the stall notification interrupt disable the abort abort notification interrupt 101 Generate a bus stall for a read while write erase enable the operation abort disable the abort notification interrupt 100 Generate a bus stall for a read while write erase enable the operation abort and the abort notification interrupt T...

Page 260: ...ield controls the prefetch algorithm used by the PFLASH controller This field defines the prefetch behavior In all situations when enabled only a single prefetch is initiated on each buffer miss or hit This field is set to 2b10 by hardware reset 00 No prefetching is performed 01 The referenced line is prefetched on a buffer miss that is prefetch on miss 1 The referenced line is prefetched on a buf...

Page 261: ...equired settings are documented in the SoC specification Higher operating frequencies require non zero settings for this field for proper Flash operation This field is set to 0b00010 by hardware reset 00000 Accesses may be initiated on consecutive back to back cycles 00001 Access requests require one additional hold cycle 00010 Access requests require two additional hold cycles 11110 Access reques...

Page 262: ... erase disable the stall notification interrupt disable the abort abort notification interrupt 110 Generate a bus stall for a read while write erase enable the stall notification interrupt disable the abort abort notification interrupt 101 Generate a bus stall for a read while write erase enable the operation abort disable the abort notification interrupt 100 Generate a bus stall for a read while ...

Page 263: ...e code Flash bank0 array at reset To temporarily change the values of any of the fields in the CFLASH_BIU2 a write to the IPS mapped register is performed To change the values loaded into the CFLASH_BIU2 at reset the word location at address 0x203E00 of the shadow region in the Flash array must be programmed using the normal sequence of operations The reset value shown in Figure 11 10 reflects an ...

Page 264: ...may be triggered by this master 16 31 MxAP Master x Access Protection x 0 1 2 7 These fields control whether read and write accesses to the Flash are allowed based on the master number of the initiating module 00 No accesses may be performed by this master 01 Only read accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses ma...

Page 265: ...re one additional hold cycle 00010 Access requests require two additional hold cycles 11110 Access requests require 31 additional hold cycles 11111 No address pipelining 3 5 19 20 BK0_WWSC Bank0 Write Wait State Control This field is used to control the number of wait states to be added to the best case Flash array access time for writes The best case Flash array access time for writes is two cycl...

Page 266: ...on results 0 MHz 23 MHz APC 0 RWSC 0 23 MHz 45 MHz APC 1 RWSC 0 45 MHz 68 MHz APC 2 RWSC 1 68 MHz 90 MHz APC 3 RWSC 2 This field is set to 0b00001 by hardware reset 00000 No additional wait states are added 00001 1 additional wait state is added 00010 2 additional wait states are added 111111 31 additional wait states are added 24 Reserved should be cleared 25 B0_P0_DPFE Bank0 Port 0 Data Prefetch...

Page 267: ...o used to invalidate the buffers This bit is cleared by hardware reset 0 The page buffers are disabled from satisfying read requests and all buffer valid bits are cleared 1 The page buffers are enabled to satisfy read requests on hits Buffer valid bits may be set when the buffers are successfully filled Offset 0x020 Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 268: ... 27 28 29 30 31 R BK0_ RWW C B0_P1_BCF G B0_P 1_DP FE B0_P 1_IPF E B0_P1_PFL M B0_P 1_BF E BK0_ RWW C 0 0 0 0 0 0 0 W Reset 1 1 1 1 1 1 1 1 Figure 11 13 PFLASH Configuration Register 2 PFCR2 Table 11 17 PFLASH Configuration Register 2 Field Descriptions Field Description 0 1 BK0_P0_BCFG Bank0 Port 0 Page Buffer Configuration This field controls the configuration of the four line buffers in the PFL...

Page 269: ...cation interrupts 17 18 B0_P1_BCFG Bank0 Port 1 Page Buffer Configuration This field controls the configuration of the four line buffers in the PFLASH controller The buffers can be organized as a pool of available resources or with a fixed partition between instruction and data buffers If enabled when a buffer miss occurs it is allocated to the least recently used buffer within the group and the j...

Page 270: ...s are enabled B0_P1_BFE 1 prefetching is triggered by any instruction fetch read access This field is ignored in the BLOCK NAME implementation 21 22 B0_P1_PFLM Bank0 Port 1 Prefetch Limit This field controls the prefetch algorithm used by the PFLASH controller This field defines the prefetch behavior In all situations when enabled only a single prefetch is initiated on each buffer miss or hit This...

Page 271: ...r this field for proper Flash operation 00000 Accesses may be initiated on consecutive back to back cycles 00001 Access requests require one additional hold cycle 00010 Access requests require two additional hold cycles 11110 Access requests require 31 additional hold cycles 11111 No address pipelining This field is ignored in single bank Flash configurations 5 9 BK1_WWSC Bank1 Write Wait State Co...

Page 272: ...ash reads while the array is busy with a program write or erase operation 0 Terminate any attempted read while write erase with an error response 111 Generate a bus stall for a read while write erase disable the stall notification interrupt disable the abort abort notification interrupt 110 Generate a bus stall for a read while write erase enable the stall notification interrupt disable the abort ...

Page 273: ...register 1 7 Reserved Read Only Write these bits has no effect and read these bits always outputs 0 8 15 DSI7 0 Data Syndrome Input 7 0 Read Write These bits represents the input of Syndrome bits of ECC logic used in the ECC Logic Check The DSI7 0 correspond to the 8 syndrome bits on a double word These bits are not accessible whenever MCR DONE or UT0 AID are low reading returns indeterminate data...

Page 274: ...equence AIS 1 is just logically sequential It should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence This bit is not accessible whenever MCR DONE or UT0 AID are low reading returns indeterminate data while writing has no effect 0 Array Integrity sequence is proprietary sequence 1 Array Integrity sequence is sequential 30 AI...

Page 275: ...st 1 register field descriptions Bit Description 0 31 DAI31 00 Data Array Input 31 0 Read Write These bits represents the input of even word of ECC logic used in the ECC Logic Check The DAI31 00 correspond to the 32 array bits representing Word 0 within the double word 0 The array bit is forced at 0 1 The array bit is forced at 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DAI6 3 DAI6 2 DAI6 1 DAI6 0 DA...

Page 276: ...0 22 MS0 21 MS0 20 MS0 19 MS0 18 MS0 17 MS0 16 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MS0 15 MS0 14 MS0 13 MS0 12 MS0 11 MS0 10 MS0 09 MS0 08 MS0 07 MS0 06 MS0 05 MS0 04 MS0 03 MS0 02 MS0 01 MS0 00 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 11 22 User Multiple Input S...

Page 277: ...le input Signature 063 032 Read Write These bits represents the MISR value obtained accumulating the bits 63 32 of all the pages read from the Flash Memory The MS can be seeded to any value by writing the UMISR1 register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MS0 95 MS0 94 MS0 93 MS0 92 MS0 91 MS0 90 MS0 89 MS0 88 MS0 87 MS0 86 MS0 85 MS0 84 MS0 83 MS0 82 MS0 81 MS0 80 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0...

Page 278: ... 18 MS1 17 MS1 16 MS1 15 MS1 14 MS1 13 MS1 12 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MS1 11 MS1 10 MS1 09 MS1 08 MS1 07 MS1 06 MS1 05 MS1 04 MS1 03 MS1 02 MS1 01 MS1 00 MS0 99 MS0 98 MS0 97 MS0 96 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Table 11 25 User Multiple Input Si...

Page 279: ...a prefetch Access protections may be applied on a per master basis for both reads and writes to support security and privilege mechanisms Throughout this discussion bkn_ is used as a prefix to refer to two signals each for each bank bk0_ and bk1_ Also the nomenclature Bx_Py_RegName is used to reference a program visible register field associated with bank x and port y 11 7 1 Basic Interface Protoc...

Page 280: ... it is first loaded into the least recently used buffer The status of this buffer is not changed to most recently used until a subsequent buffer hit occurs 11 7 4 Read Cycles Buffer Hit Single cycle read responses to the AHB are possible with the Flash BIU when the requested read access was previously loaded into one of the bank0 page buffers In these buffer hit cases read data is returned to the ...

Page 281: ...h an error This may occur due to an uncorrectable ECC error or because of improper sequencing during program erase operations When an error response is received the Flash BIU does not update or validate a page read buffer An error response may be signaled on read or write operations For more information on the specifics related to signaling of errors including Flash ECC refer to the low cost Flash...

Page 282: ... patterns of Flash accesses and allows for prefetched data to remain valid when non prefetch enabled bus masters are granted Flash access Several algorithms are available for prefetch control which trade off performance versus power They are defined by the Bx_Py_PFLM prefetch limit register field More aggressive prefetching increases power slightly due to the number of wasted discarded prefetches ...

Page 283: ...ses the state of the Flash array s bkn_fl_done output to determine if it is busy performing some type of high voltage operation namely if bkn_fl_done 0 the array is busy Specifically there are two 3 bit read while write BKn_RWWC control register fields which define the Flash BIU s response to these types of access sequences There are five unique responses that are defined by the BKn_RWWC setting o...

Page 284: ...t signal and an abort notification interrupt generated There are two abort notification interrupts one for each bank As detailed above there is a total of four interrupt requests associated with the stall while write functionality These four interrupt requests are captured as part of MCM s Interrupt Register and logically summed together to form a single request to the interrupt controller 11 7 11...

Page 285: ...ating mode The registers mentioned in these sections are detailed in Section 11 6 2 Register Descriptions 11 7 12 1 Flash Read and Write The default state of the Flash module is read The main and shadow address space can be read only in the read state The module configuration register CFLASH_MCR is always available for read The Flash module enters the read state on reset The Flash module is in the...

Page 286: ...g but attempts to program or erase these blocks do not occur since they are forced to be locked Refer to Section 11 6 2 2 Low Mid Address Space Block Locking Register CFLASH_LMLR and Section 11 6 2 3 Secondary Low Mid Address Space Block Locking Register CFLASH_SLMLR for more information 11 7 12 2 Read while write RWW The Flash core is a single partition Flash RWW is not supported within the secto...

Page 287: ...p 2 9 Write a logic 0 to the CFLASH_MCR PGM bit to terminate the program sequence The program sequence is presented graphically in Figure 11 15 The program suspend operation detailed in Figure 11 15 is discussed in Section 11 7 12 3 2 Flash Program Suspend Resume The first write after a program is initiated determines the page address to be programmed The program can be initiated with the 0 to 1 t...

Page 288: ...le Semiconductor Preliminary Subject to Change Without Notice WARNING Aborting a program operation leaves the Flash core addresses being programmed in an indeterminate data state This can be recovered by executing an erase on the affected blocks ...

Page 289: ...nd PGM 0 User Mode Read State PEG 0 Read MCR DONE 1 DONE 0 Write MCR PSUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 PGM More Words Step 8 No Yes Write MCR PGM 0 User Mode Read State Step 9 Go to Step 2 Note PEG remains valid under this condition until EHV is set high or PGM is cleared Note PSUS cannot be cleared while EHV 0 PSUS and EHV cannot b...

Page 290: ...rting an erase operation leaves the Flash core blocks being erased in an indeterminate data state This can be recovered by executing an erase on the affected blocks The erase sequence consists of the following sequence of events 1 Change the value in the CFLASH_MCR ERS bit from 0 to a 1 2 Select the block or blocks to be erased by writing ones to the appropriate registers in CFLASH_LMSR or CFLASH_...

Page 291: ... An aborted erase results in CFLASH_MCR PEG being set low indicating a failed operation The blocks being operated on before the abort contain indeterminate data The user cannot abort an erase sequence while in erase suspend WARNING Aborting an erase operation leaves the Flash core blocks being erased in an indeterminate data state This can be recovered by executing an erase on the affected blocks ...

Page 292: ...1 from the blocks being erased return indeterminate data Example 11 2 Sector Erase Suspend CFLASH_MCR 0x00000007 Set ESUS in MCR Erase Suspend do Loop to wait for DONE 1 tmp MCR Read MCR while tmp 0x00000400 Notice that there is no need to clear MCR EHV and MCR ERS in order to perform reads during erase suspend The erase operation is resumed by clearing the CFLASH_MCR ESUS bit The Flash continues ...

Page 293: ...Voltage Active Access MCR DONE Step 4 WRITE ESUS 1 Read MCR DONE 1 Erase Suspend ERS 0 User Mode Read State PEG 0 Read MCR DONE 1 DONE 0 Write MCR ESUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 Erase More Blocks Step 8 No Yes Write MCR ERS 0 User Mode Read State Step 9 EHV 0 Write MCR PGM 1 Program Step 2 Go to Step 2 Note PEG remains valid unde...

Page 294: ...ly bits 31 0 of each page 2 The second pass will scan only bits 63 32 of each page 3 The third pass will scan only bits 95 64 of each page 4 The fourth pass will scan only bits 127 96 of each page 5 The fifth pass will scan only the ECC bits 8 8 and the single and double ECC errors 2 2 of both Double Words of each page The 128 bit data and the 16 ECC data are sampled before the eventual ECC correc...

Page 295: ...Margin 0 or Margin 1 on unlocked blocks The Margin Read operation allows to unbalance the Sense Amplifiers so that all the read accesses reduce the margin vs 0 UT0 MRV 0 or vs 1 UT0 MRV 1 The results of the margin reads can be checked comparing with a previously stored expected data The Margin Read Setup operation consists of the following sequence of events 1 Set UTE in UT0 by writing the related...

Page 296: ...ogic 0 to the UT0 AIE bit Once this operation has completed all the following read accesses to the Flash Matrix will be in normal Read Mode The Wait States previously added for the Margin Read can be removed Example 11 6 Read Reset operation UT0 0xF9F99999 Set UTE in UT0 Enable User Test UT0 0x80000028 Set MRE EIE in UT0 Select Operation UT0 0x8000002A Set AIE in UT0 Operation Start do Loop to wai...

Page 297: ...x803F0000 Set DSI7 0 in UT0 Syndrome Input Data UT0 0x803F0008 Set EIE in UT0 Select ECC Logic Check UT0 0x803F000A Set AIE in UT0 Operation Start do Loop to wait for AID 1 tmp UT0 Read UT0 while tmp 0x00000001 data0 UMISR0 Read UMISR0 content expected 0x55555555 data1 UMISR1 Read UMISR1 content expected 0xAAAAAAAA data2 UMISR2 Read UMISR2 content expected 0x55555555 data3 UMISR3 Read UMISR3 conte...

Page 298: ...te User Area 0x200008 to 0x203DCF 15816 byte Reserved 0x203DD0 to 0x203DD7 8 byte NVPWD0 1 Non Volatile private censorship Password 0 1 reg 0x203DD8 to 0x203DDF 8 byte NVSCI0 1 Non Volatile System Censorship Information 0 1 0x203DE0 to 0x203DE7 8 byte Reserved 0x203DE8 to 0x203DFF 24 byte NVBIU2 3 Non Volatile Bus Interface Unit 2 3 registers 0x203E00 to 0x203E0F 16 byte Reserved 0x203E10 to 0x203...

Page 299: ... master 32 KB block powered by separate supply for standby operation Byte halfword word and doubleword addressable ECC performs single bit correctionn double bit detection 12 3 Modes of Operation 12 3 1 Normal Functional Mode Allows for reads and writes of the SRAM memory arrays 12 3 2 Standby Mode Preserves contents of the standby portion of the memory when the 1 2V power drops below the level of...

Page 300: ...39 bits each The ECC code performs single bit corrections and indicate a multiple bit error on all double bit read errors Multiple bit errors will assert an error indication in the bus cycle as well as setting the PRNCE bit in the ECSM s ESR During a write operation for 8 bit and 16 bit data a read of 32 bit data will be checked for ECC prior to merging in the write data If a correction is require...

Page 301: ... associated with the ECC are located in the ECSM See Section 18 4 1 Platform ECC Registers 32 64 bit Write Idle 0 Read 0 32 64 bit Write 0 8 16 bit Write 1 8 16 bit Write Idle 0 Read 0 32 64 bit Write 0 8 16 bit Write 1 Table 12 2 SRAM Memory Map Address MPC5634M MPC5633M MPC5632M L2SRAM_BASE 32 KB RAM Powered by Vstby 32 KB RAM Powered by Vstby 32 KB RAM Powered by Vstby L2SRAM_BASE 0x8000 62 KB ...

Page 302: ...MPC563XM Reference Manual Rev 1 302 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 303: ...s ADDRR 10 31 16 bit data bus 3 chip select Cal_CS 0 and Cal_CS 2 3 multiplexed with 2 most significant address signals Two Write Byte Enable Cal_WE 0 1 _BE 0 1 signals Possible division factors for CLKOUT 1 2 and 4 13 1 2 Unsupported Features External master mode Burst access Transfer acknowledge Bus arbitration 13 1 3 Device Specific Register Information Table 13 1 lists several register bit val...

Page 304: ... Memory Controller External Bus Interface External Master Controller CLKOUT Skyblue Line Interface AMBA AHB Lite Interface Registers Arbiter Bus Monitor Clkout Driver on SoC CAL_CS 0 3 Internal Master Arbitration Signals Primary bus only Chip Select Signals Primary bus only Chip Select Signals CAL bus only Remaining Signals Primary and CAL bus Only one set of these signals is present at EBI block ...

Page 305: ... 0 3 signals Support for Dynamic Calibration with up to 4 chip selects Four Write Byte Enable WE 0 3 BE 0 3 signals Slower speed clock modes Stop and Module Disable Modes for power savings Optional automatic CLKOUT gating to save power and reduce EMI Misaligned access support for chip select accesses only Compatible with MPC5xx external bus with some limitations 13 2 3 Modes of Operation The mode ...

Page 306: ...ports the IPI Green Line Interface Stop Mode mechanism used for MCU power management When a request is made to enter Stop Mode controlled in SoC logic outside EBI the EBI block completes any pending bus transactions and acknowledges the stop request After the acknowledgement the system clock input may be shut off by the clock driver on the MCU While the clocks are shut off the EBI is not accessibl...

Page 307: ...the internal master and the external master The memory controller supports per chip select selection of multiplexing address data through the BRx AD_MUX bit Address on Data bus multiplexing also supports the 16 bit data bus mode MCR DBM 1 and 16 bit memories ORx PS 1 The user can select which 16 data signals are used DATA 0 15 or DATA 16 31 by writing the D16_31 bit in the EBI_MCR For either setti...

Page 308: ...1 1 This column shows which signals require a weak pullup or pulldown The EBI block does not contain these pullup pulldown devices within the block They are assumed to be in another module of the MCU e g pads module ADDR 3 31 I O Address bus BB I O Bus Busy Up BDIP Output Burst Data in Progress Up BG I O Bus Grant Up BR I O Bus Request Up CLKOUT2 2 The CLKOUT signal is driven by the System Clock B...

Page 309: ...by the EBI or an external master depending on who owns the external bus This signal is driven by the EBI on all EBI mastered external burst cycles but is only sampled by burst mode memories that have a corresponding pin See Section 13 5 2 5 Burst Transfer 13 3 2 4 BG Bus Grant BG is asserted to grant ownership of the external bus to the requesting master The BG signal is only used by the EBI when ...

Page 310: ... on chip select operation 13 3 2 8 CAL_CS 0 3 Calibration Chip Selects 0 3 CAL_CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the Calibration external bus The calibration chip selects are driven only by the EBI External master accesses on the Calibration bus are not supported In all other aspects the calibration chip selects behave exact...

Page 311: ...alid until the cycle is terminated 13 3 2 12 TA Transfer Acknowledge TA is asserted to indicate that the slave has received the data and completed the access for a write cycle or returned data for a read cycle If the transaction is a burst read TA is asserted for each one of the transaction beats For write transactions TA is only asserted once at access completion even if more than one write data ...

Page 312: ... 1 is ignored by the EBI as an input for external master transactions and the size is instead determined by the SIZE field in the EBI_MCR The SIZEN bit has no effect on the EBI when it is mastering a transaction on the external bus TSIZ 0 1 is still driven appropriately by the EBI and may or may not be used by the external master depending on the SIZEN setting for the external master s EBI See Sec...

Page 313: ...y EBI signals For a description of how signals are driven by multiple devices in External Master Mode see Section 13 5 2 10 Bus Operation in External Master Mode Table 13 5 shows how each EBI signal must have its pad configured prior to operating in each of the EBI modes See Section 13 4 1 1 EBI Module Configuration Register EBI_MCR for details on the EXTM and MDIS bits Table 13 4 Signal Function ...

Page 314: ... Mode EXTM 0 MDIS 0 External Master Mode EXTM 1 MDIS 0 ADDR 3 31 X1 1 X indicates the pad configuration is a don t care because this signal s is not used by the EBI in this mode Push Pull Push Pull Three stateable2 2 These signals should be configured as Push Pull signals in the pad configuration however the EBI disables the output buffer for these pads when it does not need to drive them in Exter...

Page 315: ...RB 1 CS 0 3 0 1 1 during int master access CAL_CS 0 3 0 1 1 during int master access DATA 0 31 0 Only 1 during write access or on Address phase when Addr Data muxing is enabled OE 0 1 1 during int master access RD_WR 0 1 1 during int master access TA 0 Only 1 during chip select or cal chip select SETA 0 access TEA 0 Only 1 for 2 cycles when timeout occurs TS 0 1 1 during int master access TSIZ 0 1...

Page 316: ...BI Calibration Base Register Bank 0 EBI_CAL_BR0 EBI_BASE 0x44 EBI Calibration Option Register Bank 0 EBI_CAL_OR0 EBI_BASE 0x48 EBI Calibration Base Register Bank 1 EBI_CAL_BR1 EBI_BASE 0x4c EBI Calibration Option Register Bank 1 EBI_CAL_OR1 EBI_BASE 0x50 EBI Calibration Base Register Bank 2 EBI_CAL_BR2 EBI_BASE 0x54 EBI Calibration Option Register Bank 2 EBI_CAL_OR2 EBI_BASE 0x58 EBI Calibration B...

Page 317: ... The ACGE bit enables the EBI feature of turning off CLKOUT holding it high during idle periods in between external bus accesses 1 Automatic CLKOUT Gating is enabled 0 Automatic CLKOUT Gating is disabled EXTM External Master Mode Table 13 8 SIZE Encoding1 1 This table is not affected by width of internal AMBA bus 32 or 64 bits only by the size of the transfer DBM Size of Ext Master Transfer2 2 Thi...

Page 318: ...ernal arbitration The internal masters of the MCU have a fixed priority of 1 By default internal and external masters have equal priority See Section 13 5 2 8 2 Internal Bus Arbiter for the internal and external priority detailed description NOTE Due to the frequent IDLE gaps between transfers inherent to AMBA internal bus protocol and the EBI arbitration convention of granting the external bus to...

Page 319: ...is in 32 bit or 16 bit Data Bus Mode 1 16 bit Data Bus Mode is used 0 32 bit Data Bus Mode is used 13 4 1 2 EBI Transfer Error Status Register EBI_TESR Figure 13 3 EBI Transfer Error Status Register EBI_TESR The EBI Transfer Error Status Register contains a bit for each type of transfer error on the external bus A bit set to logic 1 indicates what type of transfer error occurred since the last tim...

Page 320: ... external bus clock resolution for the Bus Monitor See Section 13 5 1 7 Bus Monitor for more details on bus monitor operation Timeout Period 2 8 BMT external bus clock frequency BME Bus Monitor Enable This bit controls whether the bus monitor is enabled for internal to external bus cycles The BME bit is ignored treated as 0 for chip select accesses with internal TA SETA 0 1 Enable bus monitor for ...

Page 321: ...ed by the EBI during the chip select address comparison However the internal bridge of the MCU most likely requires that the chip select banks be located in memory regions corresponding to the fixed values chosen PS Port Size The PS bit determines the data bus width of transactions to this chip select bank NOTE In the case where the DBM bit in EBI_MCR is set for 16 bit Data Bus Mode the PS bit val...

Page 322: ...at burst to 32 bit external memory are supported WEBS Write Enable Byte Select This bit controls the functionality of the WE 0 3 BE 0 3 signals 1 The WE 0 3 BE 0 3 signals function as BE 0 3 0 The WE 0 3 BE 0 3 signals function as WE 0 3 TBDIP Toggle Burst Data in Progress This bit determines how long the BDIP signal is asserted for each data beat in a burst cycle See Section 13 5 2 5 1 TBDIP Effe...

Page 323: ...Option Register pair are valid The appropriate CS signal does not assert unless the corresponding V bit is set 1 This bank is valid 0 This bank is not valid 13 4 1 5 EBI Option Registers EBI_OR0 EBI_OR3 EBI_CAL_OR0 3 Figure 13 6 EBI Option Registers EBI_OR0 EBI_OR3 EBI_CAL_OR0 3 The EBI Option Registers are used to define the address mask and other attributes for the corresponding chip select AM A...

Page 324: ...first beat including the TS cycle 2 SCY external clock cycles See Section 13 6 3 1 Example Wait State Calculation for related application information BSCY Burst beats length in clocks This field determines the number of wait states external cycles inserted in all burst beats except the first when the memory controller starts handling the external memory access and thus is using SCY 0 3 to determin...

Page 325: ... access internal address space when the EBI is configured for External Master Mode in the EBI_MCR External master operations are described in detail in Section 13 5 2 10 Bus Operation in External Master Mode 13 5 1 5 Memory Controller with Support for Various Memory Types The EBI contains a memory controller that supports a variety of memory types including synchronous burst mode flash and SRAM an...

Page 326: ...gisters EBI_OR0 EBI_OR3 EBI_CAL_OR0 3 for a full description of all chip select attributes When no match is found on any of the chip select banks the default transfer attributes shown in Table 13 12 are used Table 13 12 Default Attributes for Non Chip Select Transfers CS Attribute Default Value Comment PS 0 32 bit port size BL 0 burst length is don t care since burst is disabled WEBS 0 write enabl...

Page 327: ...t size See Section 13 5 2 6 Small Accesses Small Port Size and Short Burst Length for more detail on these cases 13 5 1 7 Bus Monitor When enabled via the BME bit in the EBI_BMCR the bus monitor detects when no TA assertion is received within a maximum timeout period for external TA accesses The timeout for the bus monitor is specified by the BMT field in the EBI_BMCR Each time a timeout error occ...

Page 328: ...f the WE 0 3 BE 0 3 signals remains the same in either case The upper Write Byte Enable WE0 BE0 indicates that the upper eight bits of the data bus DATA 0 7 contain valid data during a write read cycle The upper middle Write Byte Enable WE1 BE1 indicates that the upper middle eight bits of the data bus DATA 8 15 contain valid data during a write read cycle The lower middle Write Byte Enable WE2 BE...

Page 329: ...isabled out of reset and can be enabled or disabled by the ACGE bit in the EBI_MCR NOTE This feature must be disabled for multi master systems In those cases one master is getting its clock source from the other master and needs it to stay valid continuously Table 13 13 Write Byte Enable Signals Function 1 1 This table applies to aligned internal master transfers only In the case of a misaligned i...

Page 330: ...ore assuming that an MPC5xx compatible device works with this EBI See Section 13 6 8 Summary of Differences from MPC5xx for details NOTE Due to testing and complexity concerns multi master or master slave operation between an eSys MCU and MPC5xx is not guaranteed 13 5 2 External Bus Operations The following sections provide a functional description of the external bus the bus cycles provided for d...

Page 331: ...nabled On a write cycle the master must not drive write data until after the address transfer phase is complete This is to avoid electrical contentions when switching between drivers The master must start driving write data one cycle after the address transfer cycle The master can stop driving the data bus as soon as it samples the TA line asserted on the rising edge of CLKOUT To facilitate asynch...

Page 332: ... Change Without Notice Figure 13 9 Basic Flow Diagram of a Single Beat Read Cycle MASTER EBI SLAVE asserts transfer start TS drives address and attributes receives address drives data asserts transfer acknowledge TA receives data CS access SETA yes no asserts transfer acknowledge TA ...

Page 333: ... Rev 1 Freescale Semiconductor 333 Preliminary Subject to Change Without Notice Figure 13 10 Single Beat 32 bit Read Cycle CS Access Zero Wait States CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP OE CSx 00 ...

Page 334: ... 1 334 Freescale Semiconductor Preliminary Subject to Change Without Notice Figure 13 11 Single Beat 32 bit Read Cycle CS Access One Wait State CLKOUT ADDR 3 31 TS RD_WR TSIZ 0 1 BDIP DATA 0 31 TA DATA is valid Wait State OE CSx 00 ...

Page 335: ...tates 13 5 2 4 2 Single Beat Write Flow The handshakes for a single beat write cycle are illustrated in the following flow and timing diagrams CLKOUT ADDR 3 31 TS DATA 0 31 TA input RD_WR DATA is valid TSIZ 0 1 BDIP OE CSx 00 The EBI drives address and control signals an extra cycle because it uses a latched version of the external TA 1 cycle delayed to terminate the cycle ...

Page 336: ... Notice Figure 13 13 Basic Flow Diagram of a Single Beat Write Cycle MASTER SLAVE asserts transfer start TS drives address and attributes receives address drives data asserts transfer acknowledge TA stops driving data CS access SETA yes no asserts transfer acknowledge TA receives data waits 1 clock ...

Page 337: ...ev 1 Freescale Semiconductor 337 Preliminary Subject to Change Without Notice Figure 13 14 Single Beat 32 bit Write Cycle CS Access Zero Wait States CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP WE 0 3 CSx 00 DATA is valid ...

Page 338: ...338 Freescale Semiconductor Preliminary Subject to Change Without Notice Figure 13 15 Single Beat 32 bit Write Cycle CS Access One Wait State CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 Wait State BDIP WE 0 3 CSx 00 DATA is valid ...

Page 339: ...nal bus accesses that are not part of a set of small accesses see Section 13 5 2 6 Small Accesses Small Port Size and Short Burst Length for small access timing A dead cycle refers to a cycle between the TA of a previous transfer and the TS of the next transfer CLKOUT ADDR 3 31 TS DATA 0 31 TA input RD_WR TSIZ 0 1 BDIP 00 WE 0 3 CSx DATA is valid The EBI drives address and control signals an extra...

Page 340: ... external bus do not cause any change in the timing from that shown in the previous diagrams and the two transactions are independent of each other The only exceptions to this are listed below Back to back accesses where the first access ends with an externally driven TA or TEA In these cases an extra cycle is required between the end of the first access and the TS assertion of the second access S...

Page 341: ...Rev 1 Freescale Semiconductor 341 Preliminary Subject to Change Without Notice Figure 13 17 Back to Back 32 bit Reads to the Same CS Bank CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP OE CSx 00 DATA is valid ...

Page 342: ... 1 342 Freescale Semiconductor Preliminary Subject to Change Without Notice Figure 13 18 Back to Back 32 bit Reads to Different CS Banks CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP OE CSx 00 DATA is valid CSy ...

Page 343: ...ual Rev 1 Freescale Semiconductor 343 Preliminary Subject to Change Without Notice Figure 13 19 Write After Read to the Same CS Bank ADDR 3 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP WE CSx 00 DATA is valid CLKOUT ...

Page 344: ...ev 1 344 Freescale Semiconductor Preliminary Subject to Change Without Notice Figure 13 20 Back to Back 32 bit Writes to the Same CS Bank ADDR 3 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP WE CSx 00 CLKOUT DATA is valid DATA is valid ...

Page 345: ...e Same CS Bank 13 5 2 5 Burst Transfer The EBI supports wrapping 32 byte critical doubleword first burst transfers Bursting is supported only for internally requested cache line size 32 byte read accesses to external devices that use the chip selects1 ADDR 3 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP WE CSx 00 DATA is valid CLKOUT ...

Page 346: ...rst from 16 bit port size memories taking twice as many external beats to fetch the data as compared to a 32 bit port with the same burst length The EBI can also burst from 16 bit or 32 bit memories that have a 4 word burst length BL 1 in the appropriate Base Register In this case two external 4 word burst transfers wrapping on 4 word boundary are performed to fulfill the internal 8 word request1 ...

Page 347: ...nd slave device When the TBDIP bit is set in the appropriate Base Register the timing for BDIP is altered See Section 13 5 2 5 1 TBDIP Effect on Burst Transfer for this timing Since burst writes are not supported by the EBI1 the EBI negates BDIP during write cycles 1 Except for the special case of a 32 bit non chip select access in 16 bit data bus mode See Section 13 5 2 11 Non Chip Select Burst i...

Page 348: ... 13 22 Basic Flow Diagram of a Burst Read Cycle MASTER SLAVE asserts transfer start TS drives address and attributes receives address drives data asserts transfer acknowledge TA next to last data beat yes no negate BDIP receive last data drives last data receives data assert BDIP asserts transfer acknowledge TA ...

Page 349: ...escale Semiconductor 349 Preliminary Subject to Change Without Notice Figure 13 23 Burst 32 bit Read Cycle Zero Wait States CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP 00 ADDR 29 31 000 Expects another data CSx OE DATA is valid ...

Page 350: ...efault to run burst cycles Using the default value of TBDIP 0 in the appropriate EBI Base Register results in BDIP being asserted SCY 1 cycles after the address transfer phase and being held asserted throughout the cycle regardless of the wait states between beats BSCY Figure 13 25 shows an example of the TBDIP 0 timing for a 4 beat burst with BSCY 1 CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR TSIZ 0 1...

Page 351: ...s TBDIP 0 When using TBDIP 1 the BDIP behavior changes to toggle between every beat when BSCY is a non zero value Figure 13 26 shows an example of the TBDIP 1 timing for the same 4 beat burst shown in Figure 13 25 CLKOUT TS DATA 0 31 BDIP Wait State CSx OE DATA is valid Expects another data ADDR 3 31 RD_WR TSIZ 0 1 00 ADDR 29 31 000 Wait State Wait State Wait State TA ...

Page 352: ...elect access or default burst disabled 32 bit port for non chip select access are such that the number of bytes requested by the internal master cannot all be fetched or written in one external transaction If this is the case the EBI initiates multiple transactions until all the requested data is transferred It should be noted that all the transactions initiated to complete the data transfer are c...

Page 353: ...e Write with External TA The following sections show a few examples of small accesses The timing for the remaining cases in Table 13 15 can be extrapolated from these and the other timing diagrams in this document 13 5 2 6 1 Small Access Example 1 32 bit Write to 16 bit Port Figure 13 27 shows an example of a 32 bit write to a 16 bit port requiring two 16 bit external transactions Table 13 15 Smal...

Page 354: ...al master using external TA requiring eight 32 bit external transactions Note that due to the use of external TA RD_WR does not toggle between the accesses unless that access is the end of a 64 bit boundary In this case an extra cycle is required between TA and the next TS in order to get the next 64 bits of write data internally and RD_WR negates during this extra cycle ADDR 3 31 TS DATA 0 15 TA ...

Page 355: ...For this case the address for the 2nd 4 word burst access is calculated by adding 0x10 to the lower 5 bits of the 1st address no carry and then masking out the lower 4 bits to fix them at zero ADDR 3 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP WE CSx CLKOUT A A 4 00 A 8 A 0xc 4 Four more external accesses not shown are required to complete the internal 32 byte request 1 2 3 The timing for these is the ...

Page 356: ...e Without Notice Table 13 16 Examples of 4 word Burst Addresses 1st Address Lower 5 bits of 1st Address 0x10 no carry Final 2nd Address After Masking Lower 4 Bits 0x000 0x10 0x10 0x008 0x18 0x10 0x010 0x00 0x00 0x018 0x08 0x00 0x020 0x30 0x30 0x028 0x38 0x30 0x030 0x20 0x20 0x038 0x28 0x20 ...

Page 357: ...16 Byte Bursts to 32 bit Port Zero Wait States 13 5 2 6 4 Small Access Example 4 64 bit Read to 16 bit Port Figure 13 30 shows an example of a 64 bit read to a 16 bit port requiring four 16 bit external transactions CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP 00 ADDR 29 31 000 Expects another data CSx OE DATA is valid ADDR 28 31 0000 ...

Page 358: ...sfers Table 13 17 shows the allowed sizes that an internal or external master can request from the EBI The behavior of the EBI for request sizes not shown below is undefined No error signal is asserted for these erroneous cases ADDR 3 31 TS DATA 0 15 TA RD_WR TSIZ 0 1 BDIP WE CSx CLKOUT A A 2 ABCD 10 DATA is valid Or DATA 16 31 based on D16_31 bit in EBI_MCR A 4 A 6 EFGH IJKL MNOP DATA is valid DA...

Page 359: ...not initiate the access on the internal bus The EBI requires that the portion of the data bus used for a transfer to from a particular port size be fixed A 32 bit port must reside on data bus bits 0 31 and a 16 bit port must reside on bits 0 15 In the following figures and tables the following convention is adopted The most significant byte of a 32 bit operand is OP0 and OP3 is the least significa...

Page 360: ...es required on the data bus for read cycles The bytes indicated as are not required during that read cycle Table 13 19 lists the patterns of the data transfer for write cycles when accesses are initiated by the MCU The bytes indicated as are not driven during that write cycle OP0 OP1 OP2 0 31 32 BIT 16 BIT BYTE OP0 OP1 OP2 OP3 OP0 OP1 OP2 OP3 OP3 0 31 32 bit port size OP0 OP1 OP2 OP3 OP0 OP1 OP2 O...

Page 361: ...s Table 13 18 Data Bus Requirements for Read Cycles Transfer Size TSIZ 0 1 Address 32 Bit Port Size 16 Bit Port Size1 A30 A31 D0 D7 D8 D15 D16 D23 D24 D31 D0 D72 D8 D153 Byte 01 0 0 OP0 OP0 01 0 1 OP1 OP1 01 1 0 OP2 OP2 01 1 1 OP3 OP3 16 bit 10 0 0 OP0 OP1 OP0 OP1 10 1 0 OP2 OP3 OP2 OP3 32 bit 00 0 0 OP0 OP1 OP2 OP3 OP0 OP24 OP1 OP3 1 Also applies when DBM 1 for 16 bit data bus mode 2 For address ...

Page 362: ...aits for BG to be asserted from the external arbiter For timing reasons a latched 1 cycle delayed version of BG is used by the EBI in external arbitration mode This is not a requirement of the protocol After BG assertion is received and BB is sampled negated for two cycles the MCU asserts BB and initiates the transaction An MCU operating under external arbitration may run back to back accesses wit...

Page 363: ... parked on the bus The parking feature allows the MCU to skip the bus request phase and if BB is negated assert BB and initiate the transaction without waiting for bus grant from the arbiter The priority between internal and external masters over the external bus is determined by the EARP field of the EBI_MCR See Table 13 9 for the EARP field description CLKOUT BR0 BG1 ADDR ATTR BG0 BR1 BB TS TA B...

Page 364: ...s driven out asserted by the EBI This is to avoid timing problems that would otherwise limit the frequency of operation in External Master Mode The external master is given 2 cycles to start its access after a posedge CLKOUT in which bus grant was given to it by the internal arbiter BG asserted BB negated for 2 cycles This means when BG is negated to take away bus grant from the external master th...

Page 365: ...a transaction BG 1 BB hiZ Ext Owner Ext master owns bus may or may not be running a transaction BG 0 BB hiZ MCU Bus Wait MCU owns bus for next transaction waiting for Ext Owner to negate BB from current transaction in progress BG 1 BB hiZ MCU Owner Busy MCU owns bus and is currently running a transaction BG 1 BB 0 1 Ext Bus Wait Ext master owns bus for next transaction waiting for MCU to negate BB...

Page 366: ... value to avoid potential speed paths with trying to calculate bus grant based on a late arriving internal request signal External has Higher Priority EHP 5 MCU Ext Transaction in Progress or starting next cycle ETP 6 Recent BG RBG 7 MCU Owner Idle 1 hiZ 1 X 0 0 0 X8 MCU Owner Idle MCU Owner Idle 1 hiZ X X 0 1 0 X9 Ext Owner MCU Owner Idle 1 hiZ 0 X 0 X 0 X Ext Owner MCU Owner Idle 1 hiZ 0 X X 1 0...

Page 367: ...ort an internal master cancelling its bus request If IRP is negated in this state the EBI still grants the internal master the bus as if IRP was still asserted and a few cycles may be wasted before the external master may be able to grab the bus again depending on BR BB etc according to normal transition logic 13 The default BB output is 0 for this state However anytime the EBI transitions from a ...

Page 368: ...nd IRP 0 ETP 0 and BR 0 and IRP 0 BR 1 or EHP 0 IRP 0 or BR 0 IRP 1 and BR 1 or BB 1 and RBG 0 BR 1 and ETP 1 or IRP 1 or IRP 1 and EHP 0 BR 1 and ETP 0 and IRP 0 ETP 1 and BR 0 and IRP 0 or EHP 1 BR 0 and ETP 0 and IRP 0 or EHP 1 EHP 0 ETP 1 ETP 0 and ETP 0 and and EHP 1 or BR 0 and EHP 1 or ETP External Transaction in Progress IRP Internal Request Pending EHP External has Higher Priority BR Bus ...

Page 369: ...tion If no device responds by asserting TA within the programmed timeout period BMT in EBI_BMCR after the EBI initiates the bus cycle the internal Bus Monitor if enabled asserts TEA to terminate the cycle An external device may also drive TEA when it detects an error on an external transaction TEA assertion causes the cycle to terminate and the processor to enter exception processing for the error...

Page 370: ...ng the cycle with error However proper error termination is not guaranteed for these cases so TEA must always be asserted at least 2 cycles before an internally driven TA cycle for proper error termination External TEA assertion that occurs during the same cycle that TS is asserted by the EBI is always treated as an error terminating the access regardless of SCY Table 13 22 summarizes how the EBI ...

Page 371: ...de CLKOUT ADDR 3 31 TS TA TEA RD_WR TSIZ 0 1 Slave 1 Slave 2 Slave 1 negates acknowledge signals and turns off Slave 2 allowed to drive Slave 2 negates acknowledge signals and turns off acknowledge signals DATA 0 31 The EBI drives address and control signals an extra cycle because it uses a latched version of TA 1 cycle delayed to terminate the cycle An external master is not required to do this S...

Page 372: ...erted relative to its direction when the MCU owns the bus CLKOUT ADDR 8 31 CS0 DATA 0 31 TS WE0 BE0 MCU EXTAL ADDR 8 31 DATA 0 31 CS0 TS BDIP BDIP BR BG BB TA TEA BR BG BB TA TEA MCU SDR Memory CK CS ADV WE A 0 21 DATA 0 31 BAA TSIZ 0 1 RD_WR RD_WR WE0 BE0 Only ADDR 8 29 are connected to the 32 bit SDR memory ADDR 3 7 are unused in this scenario TSIZ 0 1 configured for internal arbitration configu...

Page 373: ...lues on ADDR 3 7 are ignored 13 5 2 10 1 Address Decoding for External Accesses The external address is compared for any external master access in order to determine if EBI operation is required Since 32 address bits are available on the external bus special decoding logic is required to allow an external master to access on chip locations whose upper 8 address bits are non zero This is done by us...

Page 374: ...access The access is directed to the internal bus only if the input address matches to the internal address space The access is terminated with either TA or TEA If the access was successfully completed the MCU asserts TA and the external master can proceed with another external master access or relinquish the bus If an address or data error was detected internally the MCU asserts TEA for one clock...

Page 375: ...data External Arbitration yes no negates BG if asserted asserted from external arbiter Ext master has priority no yes negates BR if no other requests address in internal memory map no yes asserts transfer acknowledge TA drives data other shared device drives data and asserts transfer acknowledge TA receives BB negated for 2 cycles External arbiter is the EBI unless a central arbiter device is used...

Page 376: ... busy BB if no other master is driving assert transfer start TS drives address and attributes External Master EBI SLAVE request bus BR receives bus grant BG External Arbitration yes no negates BG if asserted asserted from external arbiter Ext master has priority no yes negates BR if no other requests receives BB negated for 2 cycles External arbiter is the EBI unless a central arbiter device is us...

Page 377: ...ending on which internal block is being accessed and how much internal bus traffic is going on at the time of the access Figure 13 42 External Master Read from MCU CLKOUT ADDR 8 31 TS input RD_WR TSIZ 0 1 DATA 0 31 TA output DATA is valid Minimum 2 Wait States BR input BG BB receive bus grant and bus busy negated for 2nd cycle assert BB drive address and assert TS Using the Internal arbiter BDIP I...

Page 378: ...nd cycle assert BB drive address and assert TS Using the Internal arbiter BDIP DATA 0 31 If the external master is another MCU with this EBI then BB and other control pins are turned off as shown due to use of latched TA internally This extra cycle is not required by the slave EBI DATA is valid If the external master is another MCU with this EBI then DATA remains valid as shown due to use of latch...

Page 379: ...ns for Single Master Mode with the exception that the EBI must now arbitrate for the bus before each transaction The flow and timing diagrams below show the arbitration sequence added to Figure 13 9 and Figure 13 10 for the basic single beat read case The remaining cases writes bursts etc can be obtained by adding the arbitration sequence to the flow and timing diagrams shown for Single Master Mod...

Page 380: ...usy BB if no other master is driving assert transfer start TS drives address and attributes receives address drives data asserts transfer acknowledge TA receives data CS access SETA yes no asserts transfer acknowledge TA request bus BR receives bus grant BG External Arbitration yes no negates BG if asserted asserted from external arbiter EBI has priority no yes negates BR if no other requests rece...

Page 381: ...agrams show examples of back to back accesses in External Master Mode In these examples the reads and writes shown are to a shared external memory and the EBI is assumed to be configured for internal arbitration while the external master is configured for external arbitration CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP OE CSx BR input BG BB receive bus busy negated for 2nd c...

Page 382: ...read to the same chip select bank Figure 13 47 shows an MCU read followed by an external master read to a different chip select bank Figure 13 48 shows an external master read followed by an external master write to a different chip select bank This case assumes the MCU has no higher priority internal request pending and is able to park the external master on the bus ...

Page 383: ...l Master Read followed by MCU Read to Same CS Bank CLKOUT ADDR 3 31 TS RD_WR TSIZ 0 1 DATA 0 31 TA DATA is valid BR input BG BB receive bus grant and bus busy negated for 2nd cycle Ext master starts Using the Internal arbiter BDIP read access MCU starts read access DATA is valid OE CSx Both masters off Ext master and MCU off ...

Page 384: ...ead to Different CS Bank CLKOUT ADDR 3 31 TS RD_WR TSIZ 0 1 DATA 0 31 TA DATA is valid BR input BG BB receive bus grant and bus MCU starts Using the Internal arbiter BDIP read access Ext Master starts read access DATA is valid OE CSy CSx busy negated for 2nd cycle receive bus busy negated for 2nd cycle Ext master and MCU off Ext master off Both masters off ...

Page 385: ...ed by External Master Write to Different CS Bank CLKOUT TS DATA 0 31 TA DATA is valid OE CSx DATA is valid CSy BR input BG BB ADDR 3 31 RD_WR TSIZ 0 1 BDIP External master starts read access External master starts write access receive bus grant and bus busy negated for 2nd cycle bus grant still asserted can do another access Both masters off WE ...

Page 386: ... master is expected to be another MCU with this EBI For this case a special 2 beat burst protocol is used for reads and writes so that the EBI slave can internally generate one 32 bit read or write access thus 32 bit coherent as opposed to two separate 16 bit accesses This behavior is independent of the width of the internal AMBA bus So even with a 32 bit AMBA bus 32 bit accesses are coherent just...

Page 387: ...ter 32 bit Read from MCU with DBM 1 CLKOUT ADDR 8 31 TS input RD_WR TSIZ 0 1 DATA 0 15 TA output DATA is valid Minimum 2 Wait States BR input BG BB receive bus grant and bus busy negated for 2nd cycle assert BB drive address and assert TS Using the Internal arbiter BDIP DATA is valid 00 Or DATA 16 31 based on D16_31 bit in EBI_MCR ...

Page 388: ...ter 32 bit Write to MCU with DBM 1 CLKOUT ADDR 8 31 TS input RD_WR TSIZ 0 1 DATA 0 15 TA output Minimum 3 Wait States BR input BG BB receive bus grant and bus busy negated for 2nd cycle assert BB drive address and assert TS Using the Internal arbiter BDIP 00 DATA is valid DATA is valid Or DATA 16 31 based on D16_31 bit in EBI_MCR ...

Page 389: ...oth external busses However back to back accesses can switch from one bus to the other as determined by the type of chip select each address matches The timing diagrams and protocol for the calibration bus is identical to the primary bus except that some signals are missing on the calibration bus See the device specific SoC Guide for the calibration bus signal list for a particular MCU There is an...

Page 390: ...saligned cases supported by the EBI for both 64 bit and 32 bit AMBA internal bus implementations These cases are a subset of the full set of cases allowed by the AMBA AHB V6 specification The EBI works under the assumption that all internal masters on the SoC do not produce any misaligned access cases to the EBI other than the ones below CLKOUT ADDR 3 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 ...

Page 391: ...master AHB bus uses Little Endian byte ordering EBI flips order internally HSIZE4 4 Internal signal on AHB bus 00 8 bits 01 16 bits 10 32 bits 11 64 bits HSIZE is driven according to the smallest aligned container that contains all the requested bytes This results in extra EBI external transfers in some cases HUNALIGN5 5 Internal signal on AHB bus that indicates that this transfer is misaligned wh...

Page 392: ...h Since all transfers are aligned on the external bus normal timing diagrams and protocol apply Note that the TSIZ 0 1 signals are not intended to be used for misaligned accesses so they are not specified in Table 13 24 Table 13 24 Misalignment Cases Supported by a 64 bit AMBA EBI external bus No 1 PS2 Program Size and byte offset ADDR 29 31 3 WE_BE 0 3 4 1 0 Half 0x1 0x9 000 1001 1 000 010 1011 0...

Page 393: ... 0 Doubleword 0x4 0xC 2 AHB transfers 1007 0000 000 0000 12 1 1007 110 0011 0011 000 010 0011 0011 13 0 Doubleword 0x2 0xA 2 AHB transfers 000 100 1100 0000 000 0011 13 1 010 100 110 0011 0011 0011 000 0011 14 0 Doubleword 0x6 0xE 2 AHB transfers 1106 1100 15 000 100 0000 0011 14 1 1106 0011 15 000 010 100 0011 0011 0011 1 Misaligned case number from Table 13 23 2 Port size 0 32 bits 1 16 bits 3 E...

Page 394: ... 1 1 Misaligned case number Only transfers where HUNALIGN 1 are numbered as misaligned cases The missing case numbers cannot occur on a 32 bit AMBA implementation Program Size and byte offset Address 30 31 2 3 2 Address on internal master AHB bus not necessarily address on external ADDR pins 3 Address Z is incremented by one 32 bit word compared to previous access on the AMBA bus Data Bus Byte Str...

Page 395: ...t clock This clock gap already exists for other reasons for non small access transfers so no additional clock gap is inserted for those cases See Figure 13 52 for an example of a small access read with A D multiplexing enabled 4 0 Half 0x3 2 AHB transfers 116 1110 z00 0111 4 1 116 1011 z00 0111 8 0 Word 0x1 2 AHB transfers 00 1000 z00 0111 8 1 00 10 1011 0011 z00 0111 9 0 Word 0x2 2 AHB transfers ...

Page 396: ...en in Figure 13 52 Figure 13 52 Small access 32 bit read to 16 bit port on Address Data multiplexed bus CLKOUT ADDR 3 31 TS DATA 16 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP OE CSx 10 DATA is valid Addr Addr 0x2 Addr Addr 0x2 Clock Gap While the EBI drives all of ADDR 3 31 to valid address typically only ADDR 3 15 or less are used in the system as DATA 16 31 or DATA 0 15 would be used for address an...

Page 397: ...nal accesses are being performed such as the following method Copy the code that is doing the register writes plus a return branch to internal SRAM Branch to internal SRAM to run this code ending with a branch back to external flash 13 6 2 Running with SDR Single Data Rate Burst Memories This includes FLASH and SRAM memories with a compatible burst interface BDIP is required only for some SDR memo...

Page 398: ... period 15 2ns Assume the input data spec for the MCU is 4ns number of wait states access time CLKOUT period 0 or 1 depending on setup time 50 15 2 3 with 4 4ns remaining so we need at least 3 wait states now check setup time 15 2 4 4 10 8ns this is the achieved input data setup time Since actual input setup 10 8ns is greater than the input setup spec 4 0ns 3 wait states is sufficient If the actua...

Page 399: ... Change Without Notice Figure 13 56 shows a timing diagram of a write operation to a 16 bit asynchronous memory using 3 wait states Figure 13 55 Read Operation to Asynchronous Memory Three Initial Wait States CLKOUT ADDR 3 31 TS DATA 0 31 TA 3 Wait States CSx OE WE 0 1 DATA is valid ...

Page 400: ...ite Operation to Asynchronous Memory Three Initial Wait States 13 6 4 Connecting an MCU to Multiple Memories The MCU can be connected to more than one memory at a time Figure 13 57 shows an example of how two memories could be connected to one MCU CLKOUT ADDR 3 31 TS DATA 0 31 TA 3 Wait States CSx WE 0 1 OE DATA is valid ...

Page 401: ...ernal address space when the EBI is configured for External Master Mode Since 32 bits are available on the external bus special decoding logic is required to allow ADDR 3 29 CS0 DATA 0 31 TS OE MCU CS1 CK A 0 21 CE SDR Memory D 0 31 ADV WE OE CK A 0 21 SDR Memory CE D 0 31 ADV WE OE CLKOUT WE0 BE0 BDIP BAA May or may not be connected depending on the memory used WE1 BE1 BAA Flash memories typicall...

Page 402: ...ly match up with the memory map of each internal slave 13 6 6 EBI Operation with Reduced Pinout MCUs Some MCUs with this EBI may not have all the pins described in this document pinned out for a particular package Some of the most common pins to be removed are DATA 16 31 arbitration pins BB BG BR and TSIZ 0 1 This section describes how to configure dual MCU systems for each of those scenarios as w...

Page 403: ...lave s EBI_MCR Anytime the master MCU needs to read or write the slave MCU with a different transfer size than the current value of the slave s SIZE field the master MCU must first write the slave s SIZE field with the correct size for the subsequent transaction 13 6 6 4 No Transfer Acknowledge TA Pin If an MCU has no TA pin available this restricts the MCU to chip select accesses only no MCU MCU ...

Page 404: ... A D multiplexing with a 16 bit bus and 8 additional address bits that are non multiplexed In this mode the EBI_MCR DBM must be set 1 and the EBI_BRx PS or EBI_CAL_BRx PS must also be set 1 for the 16 bit memory NOTE For systems using A D multiplexing in 16 bit mode it is recommended that the user set the D16_31 bit in the EBI_MCR so that ADDR 16 31 functions are muxed onto the DATA 16 31 pins Thi...

Page 405: ...D_WR WE0 BE0 Most memories have the LSB signified by bit 0 this must match the LSB of the MCU signified by bit 31 TSIZ 0 1 configured for internal arbitration configured for external arbitration If the memory is word addressable other bits of the data bus can be used For example a 32 bit Flash might need A 2 as the LSB where A D1 A D0 are not used for address decoding OE OE OE These refer to the D...

Page 406: ...IZ 0 1 RD_WR RD_WR WE0 BE0 Most memories have the LSB signified by bit 0 this must match the LSB of the MCU signified by bit 31 TSIZ 0 1 configured for internal arbitration configured for external arbitration If the memory is word addressable other bits of the data bus can be used For example a 32 bit Flash might need A 2 as the LSB where A D1 A D0 are not used for address decoding ADDR 8 15 ADDR ...

Page 407: ... have the LSB signified by bit 0 this must match the LSB of the MCU signified by bit 31 TSIZ 0 1 configured for internal arbitration configured for external arbitration If the memory is word addressable other bits of the data bus can be used For example a 32 bit Flash might need A 2 as the LSB where A D1 A D0 are not used for address decoding ADDR 8 15 DATA 8 15 ADDR 8 15 DATA 8 15 A 23 16 OE OE O...

Page 408: ...t Module BAM handles boot and configuration of EBI registers Open drain mode and pullup resistors no longer required for multi master systems extra cycle needed to switch between masters rationale saves customer hassle for multi master system setup at negligible performance cost Address decoding for external master accesses uses 4 bit code to determine internal slave instead of straight address de...

Page 409: ...d misaligned access support rationale some eSys cores require use of misaligned accesses for optimum performance Added calibration access support rationale support related SoC logic added to multiple eSys SoC s requested customer feature Added support for larger external address bus up to 29 bits rationale support larger external memory sizes Added support for address data multiplexing rationale n...

Page 410: ...MPC563XM Reference Manual Rev 1 410 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 411: ...rity interrupt requests in these target applications the time from the assertion of the interrupt request from the peripheral to when the processor is performing useful work to service the interrupt request needs to be minimized The INTC supports this goal by providing a unique vector for each interrupt request source It also provides 16 priorities so that lower priority ISRs do not delay the exec...

Page 412: ... software setable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS 14 2 2 Block Diagram Figure 14 1 is a block diagram of the dual core INTC In this document any features described for Processor 0 are intended to be backward compatible with the single core interrupt controller used on the eSYS family of devices ...

Page 413: ...quests vector interrupt request 1 vector table entry size update interrupt vector 1 The shaded subblocks are memory mapped registers and the non shaded subblocks are non memory mapped logic Priority Arbitrator Request Vector Encoder 512 Interrupt Acknowledge interrupt processor 1 9 Register vector Selector vector 9 lowest 512 highest priority interrupt requests vector interrupt request 512 x 6 bit...

Page 414: ...e that is the interrupt exception handler must read a register in the INTC to obtain the vector associated with the interrupt request to the processor The INTC will use software vector mode for a given processor when its associated HVEN_PRC0 or HVEN_PRC1 bit in the Section 14 5 3 INTC Block Configuration Register INTC_BCR is negated The hardware vector enable signal to either processor 0 or 1 is d...

Page 415: ... for this interrupt acknowledge the interrupt request to the processor will negate for at least one clock The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in the associated INTC_CPR_PRCx register onto the associated LIFO and updates the associated PRI in the associated INTC_CPR_PRCx register with the new priority This pushing of the PRI value ...

Page 416: ...Unrestricted INTC_BASE 0x4 Reserved INTC_BASE 0x8 INTC Current Priority Register for Processor 0 INTC_CPR_PRC0 Unrestricted INTC_BASE 0xC INTC Current Priority Register for Processor 1 INTC_CPR_PRC1 Unrestricted INTC_BASE 0x10 INTC Interrupt Acknowledge Register for Processor 0 INTC_IACKR_PRC0 Write and non speculative read1 1 When the HVEN bit in Section 14 5 3 INTC Block Configuration Register I...

Page 417: ...RC1 Vector Table Entry Size for Processor 0 and Processor 1 The VTES_PRC0 bit controls the number of 0 s to the right of INTVEC_PRC0 in Section 14 5 6 INTC Interrupt Acknowledge Register for Processor 0 INTC_IACKR_PRC0 The VTES_PRC1 bit controls the number of 0 s to the right of INTVEC_PRC1 If the contents of INTC_IACKR_PRC0 or INTC_IACKR_PRC1 are used as an address of an entry in a vector table t...

Page 418: ... pushed onto the LIFO and PRI is updated with the priority of the preempting interrupt request When Section 14 5 10 INTC Software Set Clear Interrupt Registers INTC_SSCIR0_3 INTC_SSCIR4_7 is written the LIFO is popped into the INTC_CPR_PRC0 s PRI field An exception case in hardware vector mode to this behavior is described in Section 14 3 1 2 Hardware Vector Mode The masking priority can be raised...

Page 419: ...14 3 PRI Values PRI Meaning 1111 Priority 15 highest priority 1110 Priority 14 1101 Priority 13 1100 Priority 12 1011 Priority 11 1010 Priority 10 1001 Priority 9 1000 Priority 8 0111 Priority 7 0110 Priority 6 0101 Priority 5 0100 Priority 4 0011 Priority 3 0010 Priority 2 0001 Priority 1 0000 Priority 0 lowest priority INTC_BASE 0xC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0...

Page 420: ...ress for Processor 0 VTBA_PRC0 can be the base address of a vector table of addresses of ISRs for Processor 0 The VTBA_PRC0 only uses the leftmost 20 bits when the VTES_PRC0 bit in INTC_BCR is asserted INTVEC_PRC0 0 8 Interrupt Vector for Processor 0 INTVEC_PRC0 is the vector of the peripheral or software setable interrupt request that caused the interrupt request to the processor When the interru...

Page 421: ...d in Section 14 3 1 2 Hardware Vector Mode The values and size of data written to the INTC_EOIR_PRC0 are ignored Those values and sizes written to this register neither update the INTC_EOIR_PRC0 contents or affect whether the LIFO pops For possible future compatibility write four bytes of all 0 s to the INTC_EOIR_PRC0 INTC_BASE 0x14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VTBA_PRC1 most significan...

Page 422: ..._3 INTC_SSCIR4_7 Figure 14 9 INTC Software Set Clear Interrupt Register 0 3 INTC_SSCIR0_3 INTC_BASE 0x1C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved INTC_BASE 0x20 0 1 2 3 4 5 6 7 8 9 ...

Page 423: ...Writing a 1 to CLRx will clear it Writing a 0 to CLRx will have no effect If a 1 is written to a pair SETx and CLRx bits at the same time CLRx will be asserted regardless of whether CLRx was asserted before the write SET0 SET7 Set Flag bits Writing a 1 will set the corresponding CLRx bit Writing a 0 will have no effect Each SETx always will be read as a 0 CLR0 CLR7 Clear Flag bits CLRx is the flag...

Page 424: ...igured in INTC_PSR8_11 through INTC_PSR508_511 respectively The number of peripheral interrupt requests is dependent on the SoC implementation Therefore not all versions of the INTC will have 512 sources of peripheral or software setable interrupt requests or the higher number priority select registers NOTE The PRC_SELx or PRIx field of an INTC_PSRx_x must not be modified while its corresponding p...

Page 425: ...igher than the PRI value in Section 14 5 4 INTC Current Priority Register for Processor 0 INTC_CPR_PRC0 or Section 14 5 5 INTC Current Priority Register for Processor 1 INTC_CPR_PRC1 negates before the interrupt request to the processor for that peripheral or software setable interrupt request is acknowledged the interrupt request to the processor still can assert or will remain asserted for that ...

Page 426: ...NTC Software Set Clear Interrupt Registers INTC_SSCIR0_3 INTC_SSCIR4_7 This write sets the corresponding CLRx bit which is a flag bit resulting in the interrupt request The interrupt request is cleared by writing a 1 to the CLRx bit The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the processor is four clocks 14 6 1 3 Unique Vector for Each...

Page 427: ...ed priority arbitrator subblock is asserted then it is passed as asserted to the associated vector encoder subblock If multiple interrupt requests from the associated priority arbitrator subblock are asserted then only the one with the lowest vector is passed as asserted to the associated vector encoder subblock The lower vector is chosen regardless of the time order of the assertions of the perip...

Page 428: ...re treated If the LIFO is pushed 15 or more times than it is popped the priorities first pushed are overwritten A priority of 0 would be an overwritten priority However the LIFO will pop 0 s if it is popped more times than it is pushed Therefore although a priority of 0 was overwritten it is regenerated with the popping of an empty LIFO The LIFO is not memory mapped even in debug mode or factory t...

Page 429: ...able interrupt flag bit which closely precedes the store to the INTC_EOIR_PRC0 or INTC_EOIR_PRC1 can result in that peripheral or software setable interrupt request being serviced again If this scenario can happen preventative measures can be used such as executing a Power Architecture isync instruction before the store to the INTC_EOIR_PRC0 or INTC_EOIR_PRC1 as shown in Section 14 7 2 1 Software ...

Page 430: ...the preempting peripheral or software setable interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next time the interrupt request to the associated processor is asserted In addition the value of the interrupt vector to the associated processor matches the value of the INTVEC field in the associated INTC_IACKR_PRC0 or INTC...

Page 431: ...features are not in this implementation of the INTC Table 14 5 Processor Interrupt Handshaking Compatibility Processor Interrupt Handshaking Capabilities Software Vector Mode Compatible Hardware Vector Mode Compatible No interrupt vector support Yes N A Optionally no interrupt vector or interrupt vector with interrupt acknowledge signal Yes Yes Only interrupt vector with interrupt acknowledge sign...

Page 432: ...an interrupt request to the processor is interrupt_request_initialization configure VTES_PRC0 VTES_PRC1 HVEN_PRC0 and HVEN_PRC1 in INTC_BCR configure VTBA_PRCx in INTC_IACKR_PRCx raise the PRIx fields and set the PRC_SELx fields to the desired processor in INTC_PSRx_x set the enable bits or clear the mask bits for the peripheral interrupt requests lower PRI in INTC_CPR_PRCx to zero enable processo...

Page 433: ...sumes that each interrupt_exception_handlerx only has space for four instructions and therefore a branch to interrupt_exception_handler_continuedx is needed interrupt_exception_handlerx b interrupt_exception_handler_continuedx 4 instructions available branch to continue interrupt_exception_handler_continuedx code to save SRR0 and SRR1 code to enable processor recognition of interrupts and save con...

Page 434: ...0 and outside the control of the RTOS the RTOS executes at INTC_CPR_PRCx priority 0 and while the tasks execute at different priorities under the control of the RTOS they also execute at INTC_CPR_PRCx priority 0 If a task shares a resource with an ISR and the PCP is being used to manage that shared resource then the task s priority can be elevated in the INTC_CPR_PRCx while the shared resource is ...

Page 435: ...TOS at priority 0 is executing X 0 Peripheral interrupt request 100 at priority 1 asserts Interrupt taken X 1 Peripheral interrupt request 400 at priority 4 is asserts Interrupt taken X 4 Peripheral interrupt request 300 at priority 3 is asserts X 4 Peripheral interrupt request 200 at priority 3 is asserts X 4 ISR408 completes Interrupt exception handler writes to INTC_EOIR_PRCx X 1 Interrupt take...

Page 436: ...pheral interrupt request for ISR2 has asserted As the processor is responding to the interrupt request from the INTC and as it is aborting transactions and flushing its pipeline it is possible in some SoC implementations that both of these stores will be executed ISR2 thereby thinks that it can access the data block coherently but the data block has been corrupted OSEK uses the GetResource and Rel...

Page 437: ...ISR but do have a higher priority than what the later portion of the ISR needs This priority inversion reduces the processor s ability to meet its deadlines One option is for the ISR to complete the earlier higher priority portion but then schedule through the RTOS a task to execute the later lower priority portion However some RTOSs can require a large amount of time for an ISR to schedule a task...

Page 438: ...can support Therefore the INTC does not support lowering the current priority within an ISR as a way to avoid priority inversion 14 7 10 Negating an Interrupt Request Outside of its ISR 14 7 10 1 Negating an Interrupt Request as a Side Effect of an ISR Some peripherals have flag bits which can be cleared as a side effect of servicing a peripheral interrupt request For example reading a specific re...

Page 439: ... regardless of the peripheral interrupt request s PRIx value in INTC_PSRx_x 14 7 11 Examining LIFO contents In normal mode the user does not need to know the contents of the LIFO He may not even know how deeply the LIFO is nested However if he should want to read the contents such as in debug mode they are not memory mapped The contents still can be read by popping the LIFO and reading the PRI fie...

Page 440: ...MPC563XM Reference Manual Rev 1 440 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 441: ...enabled again to recognize the external input by setting the EE bit of the MSR The prolog of the interrupt exception handler must acknowledge the interrupt request before the e200z335 is enabled again to recognize the external input Otherwise the e200z335 will attempt to service the same source of the interrupt request The INTC s LIFO is popped by writing to the INTC_EOIR The e200 s recognition of...

Page 442: ...nd disabling recognition of the external input has no restrictions Also as in software vector mode disabling recognition of the external input before popping the LIFO eases the calculation of the maximum pipe depth at the cost of postponing the servicing of the next interrupt request In hardware vector mode no IVOR is used including IVOR4 which has no effect The interrupt exception handler for eac...

Page 443: ...porates a non maskable interrupt pin called NMI and a new MSR bit to indicate whether it can be recovered or not This would generate a machine check exception set a new NMI bit in the MCSR and update the MSR new RI recoverable interrupt bit A scenario exists where the NMI could be received during processing of the critical input interrupt and this would not be recoverable 15 3 Interrupt Summary Th...

Page 444: ... Clear flag 6 INTC_SSCIR4_7_CLR7 0x007 0 7 INTC INTC_SSCIR4_7 CLR7 INTC software setable Clear flag 7 SWT_SWTIR_TIF 0x008 0 8 SWT SWTIR TIF SWT Software Watchdog Interrupt ECSM_ESR_COMB 0x009 0 9 ECSM ESR PRNCE ECSM ESR PFNCE ECSM combined interrupt request of the Platform RAM Non Correctable Error and Platform Flash Non Correctable Error interrupt requests eDMA_ERRL_ERR31_0 0x00a 0 10 eDMA DMAERR...

Page 445: ...INT16 eDMA channel Interrupt 16 eDMA_INTL_INT17 0x01c 0 28 eDMA DMAINTL INT17 eDMA channel Interrupt 17 eDMA_INTL_INT18 0x01d 0 29 eDMA DMAINTL INT18 eDMA channel Interrupt 18 eDMA_INTL_INT19 0x01e 0 30 eDMA DMAINTL INT19 eDMA channel Interrupt 19 eDMA_INTL_INT20 0x01f0 31 eDMA DMAINTL INT20 eDMA channel Interrupt 20 eDMA_INTL_INT21 0x020 0 32 eDMA DMAINTL INT21 eDMA channel Interrupt 21 eDMA_INTL...

Page 446: ...EISR EIF0 SIU External Interrupt Flag 0 SIU_EISR_EIF1 0x02f0 47 SIU SIU_EISR EIF1 SIU External Interrupt Flag 1 SIU_EISR_EIF2 0x030 0 48 SIU SIU_EISR EIF2 SIU External Interrupt Flag 2 SIU_EISR_EIF3 0x031 0 49 SIU SIU_EISR EIF3 SIU External Interrupt Flag 3 SIU_EISR_EIF15_4 0x032 0 50 SIU SIU_EISR EIF15 EIF4 SIU External Interrupt Flags 15 4 eMIOS_FLAG_F0 0x033 0 51 eMIOS eMIOSFLAG F0 eMIOS channe...

Page 447: ...PUMCR MGE2 eTPU eTPUMCR ILF1 eTPU eTPUMCR ILF2 eTPU eTPUMCR SCMMISF eTPU Global Exception eTPU_CISR_1_CIS0 0x044 0 68 eTPU eTPUCISR_1 CIS0 eTPU_1 Channel 0 Interrupt Status eTPU_CISR_1_CIS1 0x045 0 69 eTPU eTPUCISR_1 CIS1 eTPU_1 Channel 1 Interrupt Status eTPU_CISR_1_CIS2 0x046 0 70 eTPU eTPUCISR_1 CIS2 eTPU_1 Channel 2 Interrupt Status eTPU_CISR_1_CIS3 0x047 0 71 eTPU eTPUCISR_1 CIS3 eTPU_1 Chann...

Page 448: ...7 Interrupt Status eTPU_CISR_1_CIS18 0x056 0 86 eTPU eTPUCISR_1 CIS18 eTPU_1 Channel 18 Interrupt Status eTPU_CISR_1_CIS19 0x057 0 87 eTPU eTPUCISR_1 CIS19 eTPU_1 Channel 19 Interrupt Status eTPU_CISR_1_CIS20 0x058 0 88 eTPU eTPUCISR_1 CIS20 eTPU_1 Channel 20 Interrupt Status eTPU_CISR_1_CIS21 0x059 0 89 eTPU eTPUCISR_1 CIS21 eTPU_1 Channel 21 Interrupt Status eTPU_CISR_1_CIS22 0x05a 0 90 eTPU eTP...

Page 449: ...ADC command FIFO 0 command queue End Of Queue Flag eQADC_FISR0_CFFF0 0x068 0 104 eQADC eQADC_FISR0 CFFF0 eQADC Command FIFO 0 Fill Flag eQADC_FISR0_RFDF0 0x069 0 105 eQADC eQADC_FISR0 RFDF0 eQADC Receive FIFO 0 Drain Flag eQADC_FISR1_NCF1 0x06a 0 106 eQADC eQADC_FISR1 NCF1 eQADC command FIFO 1 Non Coherency Flag eQADC_FISR1_PF1 0x06b 0 107 eQADC eQADC_FISR1 PF1 eQADC command FIFO 1 Pause Flag eQAD...

Page 450: ...C eQADC_FISR4 NCF4 eQADC command FIFO 4 Non Coherency Flag eQADC_FISR4_PF4 0x07a 0 122 eQADC eQADC_FISR4 PF4 eQADC command FIFO 4 Pause Flag eQADC_FISR4_EOQF4 0x07b 0 123 eQADC eQADC_FISR4 EOQF4 eQADC command FIFO 4 command queue End Of Queue Flag eQADC_FISR4_CFFF4 0x07c 0 124 eQADC eQADC_FISR4 CFFF4 eQADC Command FIFO 4 Fill Flag eQADC_FISR4_RFDF4 0x07d 0 125 eQADC eQADC_FISR4 RFDF4 eQADC Receive...

Page 451: ...rain Flag DSPI_C_ISR_OVER 0x088 0 136 DSPI_C DSPI_ISR TFUF DSPI_C DSPI_ISR RFOF DSPI_C combined overrun interrupt request of the Transmit FIFO Underflow and Receive FIFO Overflow interrupt requests DSPI_C_ISR_EOQF 0x089 0 137 DSPI_C DSPI_ISR EOQF DSPI_C transmit FIFO End Of Queue Flag DSPI_C_ISR_TFFF 0x08a 0 138 DSPI_C DSPI_ISR TFFF DSPI_C Transmit FIFO Fill Flag DSPI_C_ISR_TCF 0x08b 0 139 DSPI_C ...

Page 452: ...AT2 OVFL eSCI_A combined interrupt request of the eSCI Status Register 1 Transmit Data Register Empty Transmit Complete Receive Data Register Full Idle line Overrun Noise Frame Error and Parity Error interrupt requests eSCI Status Register 2 Bit Error interrupt request LIN Status Register 1 Receive Data Ready Transmit Data Ready Received LIN Wakeup Signal Slave TimeOut Physical Bus Error CRC Error...

Page 453: ... Ready Transmit Data Ready Received LIN Wakeup Signal Slave TimeOut Physical Bus Error CRC Error Checksum Error Frame Complete interrupts requests and LIN Status Register 2 Receive Register Overflow Reserved 0x096 0 150 Reserved Reserved Reserved 0x097 0 151 Reserved Reserved FLEXCAN_A_ESR_BOFF _ INT 0x098 0 152 FLEXCAN_A ESR BOFF_INT FLEXCAN_A Bus Off Interrupt FLEXCAN_A_ESR_ERR_ INT 0x099 0 153 ...

Page 454: ..._A IFLAG1 BUF12I FLEXCAN_A Buffer 12 Interrupt FLEXCAN_A_IFLAG1_ BUF13I 0x0a8 0 168 FLEXCAN_A IFLAG1 BUF13I FLEXCAN_A Buffer 13 Interrupt FLEXCAN_A_IFLAG1_ BUF14I 0x0a9 0 169 FLEXCAN_A IFLAG1 BUF14I FLEXCAN_A Buffer 14 Interrupt FLEXCAN_A_IFLAG1_ BUF15I 0x0aa 0 170 FLEXCAN_A IFLAG1 BUF15I FLEXCAN_A Buffer 15 Interrupt FLEXCAN_A_IFLAG1_ BUF31_16I 0x0ab 0 171 FLEXCAN_A IFLAG1 BUF31I BUF16 I FLEXCAN_...

Page 455: ...BUF9I FLEXCAN_C Buffer 9 Interrupt FLEXCAN_C_IFLAG1_ BUF10I 0x0ba 0 186 FLEXCAN_C IFLAG1 BUF10I FLEXCAN_C Buffer 10 Interrupt FLEXCAN_C_IFLAG1_ BUF11I 0x0bb 0 187 FLEXCAN_C IFLAG1 BUF11I FLEXCAN_C Buffer 11 Interrupt FLEXCAN_C_IFLAG1_ BUF12I 0x0bc 0 188 FLEXCAN_C IFLAG1 BUF12I FLEXCAN_C Buffer 12 Interrupt FLEXCAN_C_IFLAG1_ BUF13I 0x0bd 0 189 FLEXCAN_C IFLAG1 BUF13I FLEXCAN_C Buffer 13 Interrupt F...

Page 456: ...x0cd 0 205 Reserved Reserved Reserved 0x0ce 0 206 Reserved Reserved Reserved 0x0cf0 207 Reserved Reserved Reserved 0x0d0 0 208 Reserved Reserved eMIOS_FLAG_F23 0x0d1 0 209 eMIOS eMIOSFLAG F23 eMIOS channel 23 Flag Reserved 0x0d2 0 210 Reserved Reserved Reserved 0x0d3 0 211 Reserved Reserved Reserved 0x0d4 0 212 Reserved Reserved Reserved 0x0d5 0 213 Reserved Reserved Reserved 0x0d6 0 214 Reserved ...

Page 457: ...0e1 0 225 Reserved Reserved Reserved 0x0e2 0 226 Reserved Reserved Reserved 0x0e3 0 227 Reserved Reserved Reserved 0x0e4 0 228 Reserved Reserved Reserved 0x0e5 0 229 Reserved Reserved Reserved 0x0e6 0 230 Reserved Reserved Reserved 0x0e7 0 231 Reserved Reserved Reserved 0x0e8 0 232 Reserved Reserved Reserved 0x0e9 0 233 Reserved Reserved Reserved 0x0ea 0 234 Reserved Reserved Reserved 0x0eb 0 235 ...

Page 458: ...0f80 248 Reserved Reserved Reserved 0x0f90 249 Reserved Reserved Reserved 0x0fa0 250 Reserved Reserved Reserved 0x0fb0 251 Reserved Reserved Reserved 0x0fc0 252 Reserved Reserved Reserved 0x0fd0 253 Reserved Reserved Reserved 0x0fe0 254 Reserved Reserved Reserved 0x0ff0 255 Reserved Reserved Reserved 0x100 0 256 Reserved Reserved Reserved 0x101 0 257 Reserved Reserved Reserved 0x102 0 258 Reserved...

Page 459: ...x10f0 271 Reserved Reserved Reserved 0x110 0 272 Reserved Reserved Reserved 0x111 0 273 Reserved Reserved Reserved 0x112 0 274 Reserved Reserved Reserved 0x113 0 275 Reserved Reserved Reserved 0x114 0 276 Reserved Reserved Reserved 0x115 0 277 Reserved Reserved Reserved 0x116 0 278 Reserved Reserved Reserved 0x117 0 279 Reserved Reserved Reserved 0x118 0 280 Reserved Reserved Reserved 0x119 0 281 ...

Page 460: ...d 0x123 0 291 Reserved Reserved Reserved 0x124 0 292 Reserved Reserved Reserved 0x125 0 293 Reserved Reserved Reserved 0x126 0 294 Reserved Reserved Reserved 0x127 0 295 Reserved Reserved Reserved 0x128 0 296 Reserved Reserved Reserved 0x129 0 297 Reserved Reserved Reserved 0x12a 0 298 Reserved Reserved Reserved 0x12b 0 299 Reserved Reserved Reserved 0x12c 0 300 Reserved Reserved PIT0 0x12d 0 301 ...

Page 461: ...11 Reserved Reserved Reserved 0x138 0 312 Reserved Reserved Reserved 0x139 0 313 Reserved Reserved Reserved 0x13a 0 314 Reserved Reserved Reserved 0x13b 0 315 Reserved Reserved Reserved 0x13c 0 316 Reserved Reserved Reserved 0x13d 0 317 Reserved Reserved Reserved 0x13e 0 318 Reserved Reserved Reserved 0x13f0 319 Reserved Reserved Reserved 0x140 0 320 Reserved Reserved Reserved 0x141 0 321 Reserved...

Page 462: ...x14b 0 331 Reserved Reserved Reserved 0x14c 0 332 Reserved Reserved Reserved 0x14d 0 333 Reserved Reserved Reserved 0x14e 0 334 Reserved Reserved Reserved 0x14f0 335 Reserved Reserved Reserved 0x150 0 336 Reserved Reserved Reserved 0x151 0 337 Reserved Reserved Reserved 0x152 0 338 Reserved Reserved Reserved 0x153 0 339 Reserved Reserved Reserved 0x154 0 340 Reserved Reserved Reserved 0x155 0 341 ...

Page 463: ...rved Reserved Reserved 0x161 0 353 Reserved Reserved Reserved 0x162 0 354 Reserved Reserved Reserved 0x163 0 355 Reserved Reserved Reserved 0x164 0 356 Reserved Reserved Reserved 0x165 0 357 Reserved Reserved STM1 0x166 0 358 stm_ipi_int1 STM 1 STM2 0x167 0 359 stm_ipi_int2 STM 2 STM3 0x168 0 360 stm_ipi_int3 STM 3 Reserved 0x169 0 361 Reserved Reserved Reserved 0x16A 0 362 Reserved Reserved Reser...

Page 464: ...MPC563XM Reference Manual Rev 1 464 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 465: ...nal and external reset sources and drives the RSTOUT pin The SIU is accessed by the e200z335 core through the peripheral bus 16 2 Features System configuration MCU reset configuration via external pins Pad configuration control System reset monitoring and generation Power on reset support Reset Status Register provides last reset source to software Glitch detection on reset input Software controll...

Page 466: ...stem configuration the reset controller and GPIO 16 3 2 Debug Mode SIU operation in debug mode is identical to operation in normal mode 16 4 Block Diagram Figure 16 1 is a block diagram of the SIU The signals shown are external pins to the device The SIU registers are accessed through the crossbar switch Note that the Power on Reset Detection block Pad Interface Pad Ring block and Peripheral I O C...

Page 467: ...on Table 16 1 lists the external pins used by the SIU Reset Controller RESET SIU Registers Detection GPIO RSTOUT Pad Configuration Power on Reset Peripheral I O Channels Pad Interface Pad Ring Config Reset Edge External IRQ IMUX DSPI Signals IRQ Inputs eQADC Triggers BOOTCFG1_ IRQ 8 15 IRQ 3 4 IRQ 0 IRQ 3 _ ETRIG 1 _ GPIO 212 WKPCFG_ NMI_ GPIO 213 Detects ...

Page 468: ...he System Reset Control Register SRCR 16 6 3 GPIO 0 213 General Purpose I O Pins The GPIO states from general purpose input and output The GPIO pins are generally multiplexed with other I O pin functions Each GPIO input and output is separately controlled by an 8 bit input GPDI or Table 16 1 SIU Signal Properties Name I O Type Pad Type Function Pull Up Down1 1 Internal weak pull up down The reset ...

Page 469: ... used to configure whether the eTPU and eMIOS pins are connected to internal weak pull up or weak pull down devices after reset The value latched on the WKPCFG pin at reset is stored in the Reset Status Register RSR and is updated for all reset sources except the Debug Port Reset and Software External Reset 16 6 6 IRQ 0 15 External Interrupt Request Input Pins The IRQ 0 15 connect to the SIU IRQ i...

Page 470: ...IRQx input has a corresponding flag bit in Section 16 9 5 External Interrupt Status Register SIU_EISR The flag bits for the IRQ 4 15 inputs are OR ed together to form one interrupt request to the interrupt controller OR function performed in the integration glue logic The flag bits for the IRQ 0 and IRQ 3 inputs can generate either an interrupt request to the interrupt controller or a DMA transfer...

Page 471: ...he eQADC external trigger inputs sources the SIU external interrupts and the DSPI signals that are used in the serial and parallel chaining of DSPI blocks eQADC Trigger Input Select Register SIU_ETISR External IRQ Input Select Register SIU_EIISR DSPI Input Select Register SIU_DISR IMUX Select Register 3 SIU_ISEL3 16 7 5 1 eQADC External Trigger Input Multiplexing The six eQADC external trigger inp...

Page 472: ...put signals from a DSPI block The input source for each SIU external interrupt is individually specified in the External IRQ Input Select Register SIU_EIISR An example of the multiplexing of an SIU external interrupt input is given in Figure 16 4 As shown in the figure the IRQ 0 input of the SIU can be connected to either the eMIOS 14 _IRQ 0 _eTPU_A 29 _GPIO 193 pin the DSPI_B 0 deserialized outpu...

Page 473: ...e Transfer Operation 16 8 Memory Map Table 16 2 is the address map for the SIU registers Table 16 2 SIU Address Map Address Use Register size bits SIU_BASE MCU ID Register 2 SIU_MIDR2 32 SIU_BASE 0x4 MCU ID Register SIU_MIDR 32 SIU_BASE 0x8 SIU Test Register SIU_TST 32 SIU_BASE 0xC Reset Status Register SIU_RSR 32 SIU_BASE 0x10 System Reset Control Register SIU_SRCR 32 SIU_BASE 0x14 SIU External I...

Page 474: ...6D8 SIU_BASE 0x7FF Reserved SIU_BASE 0x800 SIU_BASE 0x8E8 GPIO Pin Data Input Register 0 3 SIU_GPDI0_3 GPIO Pin Data Input Register 232 233 SIU_GPDI232_233 1 8 SIU_BASE 0x8D8 SIU_BASE 0x8FF Reserved SIU_BASE 0x900 eQADC Trigger Input Select Register SIU_ETISR 32 SIU_BASE 0x904 External IRQ Input Select Register SIU_EIISR 32 SIU_BASE 0x908 DSPI Input Select Register SIU_DISR 32 SIU_BASE 0x90C IMUX ...

Page 475: ...on S F Flash Size 1 Flash Size 2 Temp Range Rsvd Max Freq Rsvd Sup ply Status C C C C C C C C C C C S C C S C Hard Coded S F1 1 S F set with metal option 0 1 1 0 0 0 0 0 0 0 0 6 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Function Part Number ASCII Character TBD Rsvd EE Rsvd FR Status C C C C C C C C C S S C S S S C Hard Coded 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 M 0x4D Table 16 3 MCU ID Register...

Page 476: ...d for future enhancements 27 EE Indicates if Data Flash is present 1 Data Flash present 0 Data Flash not present 28 30 Rsvd Reserved for future enhancements 31 FR Indicates if Data FlexRay is present 1 FlexRay present 0 FlexRay not present Table 16 4 Flash Memory Size Flash Size 1 field Size 0h 16 Kbyte 1h 32 Kbyte 2h 64 Kbyte 3h 128 Kbyte 4h 256 Kbyte 5h 512 Kbyte 6h 1024 Kbyte 7h 2048 Kbyte n 24...

Page 477: ... Values corresponding to device packaging see Table 16 6 MCU ID Register Field Description 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 Table 16 6 MCU ID Register Field Description Bit Name Description 0 15 PARTNUM 0 15 Device part number 0x5633 Please see Table 16 7 for details on memory size 16 CSP CSP configuration 1 VertiCal 496 CSPpackage 0 standard QFP package or BGA208 package 17 21 PKG 0 4 Indicate the p...

Page 478: ...d a RESET input pin glitch flag The reset glitch flag bit RGF is cleared by writing a one to the bit A write of zero has no effect on the bit state The register can be read at all times The parameterized values of the SIU_RSR are implemented on this device as follows Asynchronous Reset Sources ARS 2 LLRS LCRS Synchronous Internal Reset Sources IRS 2 WDRS CRS PORTCFG 0 BOOTCFG0 2 The two modes of r...

Page 479: ... Checkstop Reset has occurred SWTRS Software Watchdog Timer Reset Status 1 An enabled SWT Reset has occurred 0 No enabled SWT Reset has occurred SSRS Software System Reset Status SIU_BASE 0xC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PORS ERS LLRS LCRS WDRS CRS SWTRS 0 0 0 0 0 0 0 SSRS SERF W RESET1 1 The RESET values for this register are defined for power on reset only 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 480: ... the MCU when the RESET pin is asserted for more than 2 clocks clock cycles but less than the minimum RESET assertion time of 10 consecutive clocks to cause a reset This bit is cleared by the reset controller for a valid assertion of the RESET pin or a power on reset or a write of one to the bit 1 A glitch was detected on the RESET pin 0 No glitch was detected on the RESET pin 16 9 4 System Reset ...

Page 481: ...al Reset 0 Do not generate a Software External Reset CRE Checkstop Reset Enable Writing a one to this bit enables a Checkstop Reset when the e200z335 core enters a checkstop state The CRE bit defaults to Checkstop Reset enabled If this bit is cleared it remains cleared until the next POR 1 A reset occurs when the e200z335 core enters a checkstop state 0 No reset occurs when the e200z335 core enter...

Page 482: ...o edge triggered event has occurred on the corresponding IRQx input 16 9 6 DMA Interrupt Request Enable Register SIU_DIRER The DMA Interrupt Request Enable Register allows the assertion of a DMA or interrupt request if the corresponding flag bit is set in Section 16 9 5 External Interrupt Status Register SIU_EISR The External Interrupt Request Enable bits enable the interrupt or DMA request There ...

Page 483: ... DMA Interrupt Request Select Register allows selection between a DMA or interrupt request for events on the IRQ0 and IRQ3 inputs Figure 16 11 DMA Interrupt Request Select Register SIU_DIRSR DIRSx DMA Interrupt Request Select x This bit selects between a DMA or interrupt request when an edge triggered event occurs on the corresponding IRQx input SIU_BASE 0x18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ...

Page 484: ...ster SIU_ORER The Overrun Request Enable Register contains bits to enable an overrun if the corresponding flag bit is set in the SIU_OSR If any Overrun Request Enable bit and the corresponding flag bit is set the single combined overrun request from the SIU to the interrupt controller is asserted Figure 16 13 Overrun Request Enable Register SIU_ORER SIU_BASE 0x20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 485: ...ng edge triggered events on the NMI input 1 Rising edge event is enabled 0 Rising edge event is disabled IREEx IRQ Rising Edge Event Enable x This bit enables rising edge triggered events on the corresponding IRQx input 1 Rising edge event is enabled 0 Rising edge event is disabled 16 9 11 External IRQ Falling Edge Event Enable Register SIU_IFEER The External IRQ Falling Edge Event Enable Register...

Page 486: ...nputs The Digital Filter Length field specifies the number of system clocks that define the period of the digital filter Figure 16 16 IRQ Digital Filter Register SIU_IDFR DFL 0 3 Digital Filter Length This field defines the digital filter period on the IRQx inputs according to Equation 16 1 SIU_BASE 0x2C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R NMIFE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 ...

Page 487: ...bits must be set accordingly IBE 1 for input and OBE 1 for output For I O functions that change direction dynamically such as the external data bus switching between input and output is handled internally and the IBE and OBE bits have no effect For all PCRs where GPIO function is available on the pin if the pin is configured as an output and the IBE bit is set the actual value of the pin will be r...

Page 488: ...ourth Pin Function PA Field Definition PA Field Pin Function 000 GPIO 001 Primary Function 010 Alternate Function 011 Primary Function 100 Second Alternate Function 101 Reserved 110 Reserved 111 Reserved Table 16 11 Fifth Pin Function PA Field Definition PA Field Pin Function 0000 GPIO 0001 Primary Function 0010 Alternate Function 0011 Primary Function 0100 Second Alternate Function 0101 Reserved ...

Page 489: ...l SRC field and others contain a Drive Strength Control DSC field Slew rate control pertains to pins with slow or medium I O pad types Drive strength control pertains to pins with the fast I O pad type The DSC field for all PCRs with drive strength control is defined in Table 16 12 The SRC field for all PCRs with slew rate control is defined in Table 16 13 16 9 13 1 Pad Configuration Register 83 S...

Page 490: ... no effect When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set to one 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 ...

Page 491: ...hen configured as CNTX or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set to one 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 ...

Page 492: ...no effect Setting the IBE bit to zero reduces power consumption When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register The IBE bit must be set to one for GPI when configured as inputs 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET ...

Page 493: ...nfigured as TXD the IBE bit has no effect When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set to one 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0...

Page 494: ...for slave operation When configured as GPO the OBE bit should be set to one IBE2 2 When configured as SCK in slave operation the IBE bit should be set to one When configured as SCK in master operation or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set...

Page 495: ...the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set to one 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved SIU_BASE 0x112 0 1 2 3 4 ...

Page 496: ...gured as PCS_B the IBE bit has no effect When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set to one 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 ...

Page 497: ...ured as PCS the IBE bit has no effect When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set to one 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0...

Page 498: ...ect When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set to one 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0...

Page 499: ... SIU_BASE 0x126 SIU_BASE 0x12C 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA 0 1 OBE1 1 The OBE bit must be set to one for both eTPU_A 1 4 and GPO 115 118 when configured as outputs When configured as eTPU_A 13 16 the OBE bit has no effect IBE2 2 The IBE bit must be set to one for both eTPU_A 1 4 and GPO 115 118 when configured as inputs When configured as eTPU_A 13 16 or when eTPU_A 1 4 or...

Page 500: ...and GPO 119 when configured as outputs When configured as eTPU_A 17 the OBE bit has no effect IBE2 2 The IBE bit must be set to one for both eTPU_A 5 and GPO 119 when configured as inputs When eTPU_A 17 or when eTPU_A 5 or GPO 119 are configured as outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 ODE HYS SRC 0 1 3 3 On the LVDS pads these bits a...

Page 501: ...PO 120 when configured as outputs When configured as eTPU_A 18 the OBE bit has no effect IBE2 2 The IBE bit must be set to one for both eTPU_A 6 and GPO 120 when configured as inputs When eTPU_A 18 or when eTPU_A 6 or GPO 120 are configured as outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 ODE HYS SRC 0 1 3 3 On the LVDS pads these bits are us...

Page 502: ...onfigured as outputs When configured as eTPU_A 6 and eTPU_A 19 the OBE bit has no effect IBE2 2 The IBE bit must be set to one for both eTPU_A 7 and GPO 121 when configured as inputs When eTPU_A 6 and eTPU_A 19 or when eTPU_A 7 or GPO 121 are configured as outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 ODE HYS SRC 0 1 3 3 On the LVDS pads thes...

Page 503: ...d lvds_opt1 inputs of the LVDS pads see Table 529 LVDS Pads Voltage Swing in Chapter 27 Deserial Serial Peripheral Interface DSPI In the other pad types they assume the Slew Rate Control functionality WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U4 4 The weak pull up down selection at reset for the eTPU_A 8 pin is determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 ...

Page 504: ...GPO outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 3 The weak pull up down selection at reset for the eTPU_A 12 pin is determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemen...

Page 505: ... eTPU_A 14 or GPO outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 3 The weak pull up down selection at reset for the eTPU_A 14 pin is determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 506: ...t be set to one for both eTPU_A and GPO when configured as inputs When configured as eTPU_A or GPO outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U4 4 The weak pull up down selection at reset for the eTPU_A 16 pin is determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26 27 2...

Page 507: ... must be set to one for both eTPU_A and GPIO when configured as inputs When configured as eTPU_A or GPO outputs the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U4 4 The weak pull up down selection at reset for the eTPU_A 18 pin is determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26...

Page 508: ...sponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for both eTPU_A 20 21 and GPIO 134 135 when configured as inputs 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 3 The weak pull up down selection at reset for the eTPU_A 20 21 pins are determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 ...

Page 509: ... alternate function and then use the register SIU_PCR139 to program the SCK_LVDS characteristics drive strength using the slew rate field SIU_BASE 0x152 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 PA 0 2 OBE1 1 The OBE bit must be set to one for both eTPU_A 23 and GPIO 137 when configured as outputs IBE2 2 When configured as RQ or GPO the IBE bit may be set to one to reflect the pin state in the...

Page 510: ...o one for GPIO 138 when configured as output IBE2 2 When configured as RQ or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for GPIO 138 when configured as input 0 0 ODE HYS SRC 0 1 3 3 On the LVDS pads these bits are used to allow the control of output voltage swing ...

Page 511: ... to one for GPIO 139 when configured as output IBE2 2 When configured as RQ or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for GPIO 139 when configured as input 0 0 ODE HYS SRC 0 1 3 3 On the LVDS pads these bits are used to allow the control of output voltage swin...

Page 512: ...o one for GPIO 140 when configured as output IBE2 2 When configured as RQ or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for GPIO 140 when configured as input 0 0 ODE HYS SRC 0 1 3 3 On the LVDS pads these bits are used to allow the control of output voltage swing ...

Page 513: ... bits are used to allow the control of output voltage swing They are connected to the lvds_opt0 and lvds_opt1 inputs of the LVDS pads see Table 529 LVDS Pads Voltage Swing in Chapter 27 Deserial Serial Peripheral Interface DSPI In the other pad types they assume the Slew Rate Control functionality WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U4 4 The weak pull up down selection at reset for the e...

Page 514: ...A output or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for eTPU_A or GPIO when configured as input 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 3 The weak pull up down selection at reset for the eTPU_A 30 pin is determined by the WKPCFG pin...

Page 515: ...et to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for eMIOS or GPIO when configured as input 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 3 The weak pull up down selection at reset for the eMIOS 0 pin is determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26 27 28...

Page 516: ...o one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for eMIOS or GPIO when configured as input 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 3 The weak pull up down selection at reset for the eMIOS 4 pins are determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26 27 28 2...

Page 517: ...190 when configured as outputs IBE2 2 When configured as eMIOS or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for both eMIOS 10 11 and GPIO 189 190 when configured as inputs 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 3 The weak pull up dow...

Page 518: ...n state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption The IBE bit must be set to one for GPIO 193 when configured as inputs 0 0 ODE HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 U3 3 The weak pull up down selection at reset for the eMIOS 14 pins is determined by the WKPCFG pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0...

Page 519: ...F function applies only during reset The PA field should be set to 0b010 for IRQ 4 set to 0b100 for ETRIG 0 and set to 0b000 for GPIO 208 OBE2 2 When configured as PLLREF or IRQ or ETRIG the OBE bit has no effect When configured as GPO the OBE bit should be set to one IBE3 3 When configured as PLLREF or IRQ or ETRIG the IBE bit has no effect When configured as GPO the IBE bit may be set to one to ...

Page 520: ...d as GPO the OBE bit should be set to one IBE3 3 When configured as BOOTCFG1 or IRQ or IRQ the IBE bit has no effect When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register Setting the IBE bit to zero reduces power consumption When configured as GPI the IBE bit should be set to one 0 0 ODE HYS4 4 When configured as IRQ the HYS bit should be ...

Page 521: ...ers are enabled disabled based on PA selection Both input and output buffer disabled for AN 12 function Output buffer only enabled for MA 0 and SDS functions 0 0 0 0 ODE 0 SRC 0 1 0 0 W RESET 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 14 PCR215 PA Field ...

Page 522: ...U_A 29 pin The AN 15 function is an analog pin on this device This register allows selection of the FCK function Table 16 15 PCR216 PA Field Definition PA Field Pin Function 00 SDO 01 eTPU_A 21 10 MA 1 11 AN 13 SIU_BASE 0x1F2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 PA 0 2 1 1 Input and output buffers are enabled disabled based on PA selection Both input and output buffer disabled for AN 14 f...

Page 523: ... SIU_BASE 0x1F6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA 0 1 1 1 The primary function is not selected by PA when the pin is a Nexus signal instead it is activated by the Nexus controller ipp_port_en_rpm The only PA valid value is 00 all other values are reserved The selection of MCKO or CLKOUT is made regardless the PA value OBE2 2 When configured as MCKO the OBE has no effect When confi...

Page 524: ... 0 0 0 HYS SRC 0 1 WPE3 3 The WPE bit should be set to zero when configured as an analog input or MA 2 and set to one when configured as SDI WPS4 4 The WPS bit should be set to one when configured as SDI W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved SIU_BASE...

Page 525: ...figured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register When configured as GPI the IBE bit should be set to one 0 0 0 HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved SIU_BASE 0x1FE 0 1 2 3 4 ...

Page 526: ...figured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register When configured as GPI the IBE bit should be set to one 0 0 0 HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved SIU_BASE 0x202 0 1 2 3 4 ...

Page 527: ...as GPO the OBE bit should be set to one IBE3 3 When configured as GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register When configured as GPI the IBE bit should be set to one 0 0 0 HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 528: ...the function and drive strength of the EVTI_eTPU_A 2 _GPIO 231 pin SIU_BASE 0x20A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 OBE 0 DSC 0 1 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved SIU_BASE 0x20C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 529: ...sponding GPDI register When configured as GPI the IBE bit should be set to one 0 0 0 HYS SRC 0 1 WPE WPS W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved SIU_BASE 0x210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA 0 1 1 1 The primary function is not selec...

Page 530: ...r SIU_PCR340 SIU_BASE 0x2E0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 DSC 0 1 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved SIU_BASE 0x2E4 SIU_BASE 0x2E6 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA 0 0 DSC 0 1 0 0 0 0 0 0...

Page 531: ...ble and byte enable functions Figure 16 91 CAL_RD_WR CAL_WE 0 1 BE 0 1 and CAL_OE Pad Configuration Register SIU_PCR342 16 9 13 76 Pad Configuration Register 343 SIU_PCR343 The SIU_PCR343 register controls the drive strength of the CAL_TS_ALE pin SIU_BASE 0x2EA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 DSC 0 1 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 16 17 18 19 20 21 22 2...

Page 532: ... drive strength of the CAL_ADDR 16 27 _CAL_MDO 0 11 CAL_ADDR 28 29 _CAL_MSEO 0 1 and CAL_ADDR 30 _CAL_EVTI pins Multiple pins are controlled by this PCR SIU_BASE 0x2EE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA 0 0 DSC 0 1 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 533: ...GPIO pin Each byte of a register drives a single external GPIO pin which allows the state of the pin to be controlled independently from other GPIO pins Writes to the SIU_GPDOx_x registers have no effect on pin states if the pins are configured as inputs by the associated Pad Configuration Registers The SIU_GPDOx_x register values are automatically driven to the GPIO pins without software update i...

Page 534: ...t on the external GPIO pin Each byte of a register drives a single external GPIO pin which allows the state of the pin to be controlled independently from other GPIO pins Writes to the SIU_GPDOx_x registers have no effect on pin states if the pins are configured as inputs by the associated Pad Configuration Registers The SIU_GPDOx_x register values are automatically driven to the GPIO pins without...

Page 535: ...GPIO 213 pin Gaps exist in this memory space where the pin is not available in the package The SIU_GPDIx_x registers are read only registers that allow software to read the input state of an external GPIO pin Each byte of a register represents the input state of a single external GPIO pin If the GPIO pin is configured as an output and the input buffer enable IBE bit is set in the associated Pad Co...

Page 536: ...ETISR The eQADC Trigger Input Select Register SIU_ETISR selects the source for the eQADC trigger inputs SIU_BASE 0x853 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 PDI 83 0 0 0 0 0 0 0 PDI 84 W RESET 0 0 0 0 0 0 0 U 0 0 0 0 0 0 0 U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 PDI 85 0 0 0 0 0 0 0 PDI 86 W RESET 0 0 0 0 0 0 0 U 0 0 0 0 0 0 0 U Unimplemented or Reserved S...

Page 537: ...to Table 16 19 SIU_BASE 0x900 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TSEL5 0 1 TSEL4 0 1 TSEL3 0 1 TSEL2 0 1 TSEL1 0 1 TSEL0 0 1 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 17 TSEL5 Field Definition TSEL5 Field eQADC Trigger 5 Input 00 eT...

Page 538: ...s Figure 16 103 External IRQ Input Select Register SIU_EIISR Table 16 20 TSEL2 Field Definition TSEL2 Field eQADC Trigger 2 Input 00 eTSEL2 01 eTPU_A 29 channel 10 eMIOS 15 channel 11 ETRIG 0 pin Table 16 21 TSEL1 Field Definition TSEL1 Field eQADC Trigger 1 Input 00 eTSEL1 01 eTPU_A 31 channel 10 eMIOS 11 channel 11 ETRIG 1 pin Table 16 22 TSEL0 Field Definition TSEL0 Field eQADC Trigger 0 Input ...

Page 539: ...L12 field according to Table 16 26 Table 16 23 ESEL15 Field Definition ESEL15 Field IRQ 15 Input 00 IRQ 15 pin 01 DSPI_B 15 serialized input 10 DSPI_C 0 serialized input 11 reserved DSPI_D 1 serialized input Table 16 24 ESEL14 Field Definition ESEL14 Field IRQ 14 Input 00 IRQ 14 pin 01 DSPI_B 14 serialized input 10 DSPI_C 15 serialized input 11 reserved DSPI_D 0 serialized input Table 16 25 ESEL13...

Page 540: ...EL8 field according to Table 16 30 Table 16 27 ESEL11 Field Definition ESEL11 Field IRQ 11 Input 00 IRQ 11 pin 01 DSPI_B 11 serialized input 10 DSPI_C 12 serialized input 11 reserved DSPI_D 13 serialized input Table 16 28 ESEL10 Field Definition ESEL10 Field IRQ 10 Input 00 IRQ 10 pin 01 DSPI_B 10 serialized input 10 DSPI_C 11 serialized input 11 reserved DSPI_D 12 serialized input Table 16 29 ESE...

Page 541: ...Select 4 The IRQ 4 input is specified by the ESEL4 field according to Table 16 34 Table 16 31 ESEL7 Field Definition ESEL7 Field IRQ 7 Input 00 IRQ 7 pin 01 DSPI_B 7 serialized input 10 DSPI_C 8 serialized input 11 reserved DSPI_D 9 serialized input Table 16 32 ESEL6 Field Definition ESEL6 Field IRQ 6 Input 00 Disabled mux output is 1 b0 01 DSPI_B 6 serialized input 10 DSPI_C 7 serialized input 11...

Page 542: ...t Register SIU_DISR register specifies the source of each DSPI data input slave select clock input and trigger input to allow serial and parallel chaining of the DSPI blocks Table 16 35 ESEL3 Field Definition ESEL3 Field IRQ 3 Input 00 IRQ 3 pin 01 DSPI_B 3 serialized input 10 DSPI_C 4 serialized input 11 reserved DSPI_D 5 serialized input Table 16 36 ESEL2 Field Definition ESEL2 Field IRQ 2 Input...

Page 543: ... 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 SIN SELB 0 1 SS SELB 0 1 SCK SELB 0 1 TRIG SELB 0 1 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SIN SELC 0 1 SS SELC 0 1 SCK SELC 0 1 TRIG SELC 0 1 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 39 SINSELB Field Definition SINSELB Field DSPI_B Data Input 00 SIN_B_PCS_C 2 _...

Page 544: ...lect The source of the clock input of DSPI_C when in slave mode is specified by the SCKSELC field according to Table 16 45 Table 16 42 TRIGSELB Field Definition TRIGSELB Field DSPI_B Trigger Input 00 Reserved 01 Reserved 10 DSPI_C_CS 4 11 reserved DSPI_D_CS 4 not available Table 16 43 SINSELC Field Definition SINSELC Field DSPI_C Data Input 00 PCS_A 2 _SIN_C_GPIO 108 pin 01 Reserved 10 SOUT_B 11 S...

Page 545: ...00 Reserved 01 Reserved 10 DSPI_B_CS 4 11 reserved DSPI_D_CS 4 not available SIU_BASE 0x90C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved eTSEL5 0 4 eTSEL4 0 4 eTSEL3 0 3 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R eTS EL3 4 eTSEL2 0 4 eTSEL1 0 4 eTSEL0 0 4 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 47 eTSEL Encoding ...

Page 546: ...exus disable input signal is negated CRSE Calibration Reflection Suppression Enable The CRSE bit enables the suppression of reflections from the EBI s calibration bus onto the non calibration bus The EBI drives some outputs to both the calibration and non calibration busses When CRSE is asserted the values driven onto the calibration bus pins will not be reflected onto the non calibration bus pins...

Page 547: ...the SIU_ECCR are read write and are reset by the IP Green Line asynchronous reset signal Figure 16 107 External Clock Control Register SIU_ECCR EBTS External Bus Tap Select The EBTS bit changes the phase relationship between the system clock and CLKOUT Changing the phase relationship so that CLKOUT is advanced in relation to system clock increases the output hold time of the external bus signals t...

Page 548: ...y 4 there is no guarantee that the switch will be glitchless 16 9 23 Compare A High Register The SIU_CMPAH register holds the 32 bit value that is compared against the value in the SIU_CMPBH register The CMPAH field is read write and is reset by the IP Green Line synchronous reset signal Figure 16 108 Compare A High Register SIU_CMPAH 16 9 24 Compare A Low Register The SIU_CMPAL register holds the...

Page 549: ... Register The SIU_CMPBL register holds the 32 bit value that is compared against the value in the SIU_CMPAL register The CMPBL field is read write and is reset by the IP Green Line synchronous reset signal SIU_BASE 0x98C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPAL W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CMPAL W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 550: ...3 14 15 R W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R By pass SYS CLKDIV 0 1 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 16 50 System Clock Register Field Descriptions Field Description 0 26 Reserved 27 Bypass bit 1 system clock divider is not bypassed 0 system clock divider is bypassed 28 29 SYSCLKDIV 0 1 System Clock Divid...

Page 551: ...to various modules Each bit will drive a separate ipg_stop output of the SIU These outputs will be connected as shown in Table 16 51 Figure 16 113 Halt Register SIU_HLT SIU_BASE 0x9A4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R HLT W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R HLT W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved ...

Page 552: ... Register Field Descriptions Table 16 51 HALT Register Field Descriptions Field Description 0 31 HLT Halt Selects The HLT bits halt specific modules Each bit corresponds to a separate module as mapped below 0 rsvd 1 rsvd 2 rsvd for FlexRay1 3 rsvd for eDMA1 4 rsvd 5 eTPU_A 6 NPC 7 EBI 8 eQADC_A 9 rsvd MLB1 10 eMIOS_A 11 DECFIL 12 rsvd for IIC_A1 13 PIT 14 rsvd for FlexCAN_F1 15 rsvd for FlexCAN_E1...

Page 553: ...ACK Halt Acknowledge The HLTACK bits acknowledge halt for specific modules Each bit corresponds to a separate module as mapped below 0 rsvd 1 rsvd 2 rsvd for FlexRay1 3 rsvd for eDMA1 4 rsvd 5 eTPU_A 6 NPC 7 EBI 8 eQADC_A 9 rsvd MLB1 10 eMIOS_A 11 DECFIL 12 rsvd for IIC_A1 13 PIT 14 rsvd for FlexCAN_F1 15 rsvd for FlexCAN_E1 16 rsvd for FlexCAN_D1 17 FlexCAN_C 18 rsvd for FlexCAN_B1 19 FlexCAN_A 2...

Page 554: ...MPC563XM Reference Manual Rev 1 554 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 555: ... Table 17 1 shows the reset values for several register fields on this device 17 2 Introduction This chapter describes the features and functions of the FMPLL module 17 2 1 Overview The frequency modulated phase locked loop FMPLL allows the user to generate high speed system clocks from a crystal oscillator or from an external clock generator Furthermore the FMPLL supports programmable frequency m...

Page 556: ...e with PLL on or off Two normal modes crystal or external reference Programmable frequency modulation Triangle wave modulation Register programmable modulation frequency and depth Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions User selectable ability to generate an interrupt request upon loss of lock ...

Page 557: ... the Clock Quality Monitor CQM will inhibit the system clock and keep system reset asserted while the crystal oscillator has not stabilized The PLLREF input must be kept stable during the whole period while system reset is asserted 17 2 3 1 Bypass Mode with Crystal Reference In the bypass mode with crystal reference the FMPLL is completely bypassed and the system clock is driven from the crystal o...

Page 558: ...stal that is within the appropriate frequency range the crystal manufacturer recommended external support circuitry and short signal route from the MCU to the crystal In normal mode with crystal reference the FMPLL can generate a frequency modulated clock or a non modulated clock locked on a single frequency The modulation rate modulation depth output divider RFD and whether the FMPLL is modulatin...

Page 559: ...at the beginning of the reset cycle and then kept stable for the whole reset duration XTAL O Crystal oscillator Output for an external crystal oscillator EXTAL_EXTCLK I O Crystal Oscillator External Clock Input This pin is the input for an external crystal oscillator or an external clock source The function of this pin is determined by the CLKCFG 2 bit of the ESYNCR1 register which reset value is ...

Page 560: ...this model it is possible to change the FMPLL operating mode back and forth between bypass and normal modes by programming the ESYNCR1 CLKCFG field The reset value of the ESYNCR1 EMODE bit is determined by the SoC integration This bit is write once After set to one further write attempts to this bit will have no effect 17 4 2 1 Synthesizer Control Register SYNCR This register is provided for backw...

Page 561: ...divider This 3 bit field controls a divider at the output of the FMPLL The value specified by the RFD bits establishes the division factor applied to the FMPLL frequency 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Invalid 1xx Invalid 13 LOCEN Loss of clock enable The LOCEN bit determines if the loss of clock function is operational This bit only has effect in normal mode In bypass mode the...

Page 562: ...re setting the LOLIRQ bit otherwise an interrupt is immediately asserted The interrupt request only happens in normal mode therefore the LOLIRQ bit has no effect in bypass mode See Section 17 5 3 Lock Detection 0 Ignore loss of lock Interrupt not requested 1 Enable interrupt request upon loss of lock 18 LOCIRQ Loss of clock interrupt request The LOCIRQ bit enables a loss of clock interrupt request...

Page 563: ...L is in bypass mode because in bypass the VCO clock is not monitored and a loss of clock on the reference clock causes reset See Section 17 5 4 Loss of Clock Detection 0 No loss of clock detected Clocks are operating normally 1 Loss of clock detected Clocks are not operating normally 24 MODE Mode of operation This bit indicates whether the FMPLL is working in bypass mode or normal mode The reset v...

Page 564: ... the PREDIV or MFD fields of the SYNCR are changed in legacy mode or when EMODE EPREDIV EMFD or CLKCFG 1 2 are changed in enhanced mode and then asserted again when the PLL regains lock If operating in bypass mode the LOCK bit is still asserted or negated when the FMPLL acquires or loses lock 0 FMPLL is unlocked 1 FMPLL is locked 29 LOCF Loss of clock flag This bit provides the interrupt request f...

Page 565: ...ntrolled by ESYNCR1 ESYNCR2 1 3 CLKCFG Clock configuration This 3 bit field is used to change the operating mode of the FMPLL Bit 2 is not writable to zero while bit 1 is 1 The reset state of bit 3 is determined by the state of the PLLREF pin 000 Bypass mode with external reference and PLL off 001 Bypass mode with crystal reference and PLL off 010 Bypass mode with external reference and PLL runnin...

Page 566: ...Invalid Offset 0x000C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 LOC EN LOL RE LOC RE LOL IRQ LOC IRQ 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERFD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Reset value is determined by the SoC integration Figure 17 5 Enhanced Synthesizer Control R...

Page 567: ...occur if the reference clock fails even if LOCRE 0 or even if LOCEN 0 The LOCRE bit has no effect in bypass mode with external reference In this mode the reference clock is not monitored at all See Section 17 5 4 2 Loss of Clock Reset 0 Ignore loss of clock Reset not asserted 1 Assert reset on loss of clock 11 LOLIRQ Loss of lock interrupt request The LOLIRQ bit enables a loss of lock interrupt re...

Page 568: ...sy processing the previous change on the SYNFMMR register write access to the register is not possible 1 MODEN Modulation enable This bit enables the frequency modulation 0 Frequency modulation disabled 1 Frequency modulation enabled 2 MODSEL Modulation selection This bit selects whether modulation will be centered around the nominal frequency or spread below the nominal frequency 0 Modulation cen...

Page 569: ...d ESYNCR2 registers according to the following equation When programming the FMPLL be sure not to violate the maximum system clock frequency or max min VCO frequency specification Furthermore the PREDIV or EPREDIV values must not be set to any value that causes the input frequency to the phase detector to go below 4 MHz The LOCK flag is immediatly negated after any of the following events 1 In leg...

Page 570: ...itor the reference and feedback clocks to determine when the system has acquired frequency lock Once the FMPLL has locked the counters continue to monitor the reference and feedback clocks and will report if when the FMPLL has lost lock The FMPLL registers provide the flexibility to select whether to generate an interrupt assert system reset or do nothing in the event that the FMPLL loses lock Los...

Page 571: ...n their frequencies stay within the limits for 3 consecutive measuring cycles In the event either of the clocks fall outside the expected window a loss of clock condition is reported The FMPLL can be programmed to switch the system clock to a backup clock in the event of such a failure Additionally the user may select to have the system enter reset assert an interrupt request or do nothing if when...

Page 572: ...il will force a reset In bypass mode with external reference no backup clock selection occurs if the reference fails 17 5 4 2 Loss of Clock Reset When a loss of clock condition is recognized a system reset may be asserted depending on the clock operating mode and control bits in the FMPLL registers as shown in Table 17 13 The LOCF and LOC bits in SYNSR are cleared after reset therefore another mea...

Page 573: ...e asserted depending on the clock operating mode and control bits in the FMPLL registers as shown in Table 17 14 LOCEN and LOCIRQ have no effect in bypass mode If the reference fails in bypass mode with crystal reference a system reset is asserted instead of an interrupt request If the reference fails in bypass with external reference no reset or interrupts are generated Furthermore no reset or in...

Page 574: ...k Interrupt Request Operating Mode LOCEN1 1 LOCEN is the loss of clock enable bit in either SYNCR or ESYNCR2 depending on the ESYNCR1 EMODE bit LOCIRQ2 2 LOCIRQ is the loss of clock interrupt enable bit in either SYNCR or ESYNCR2 depending on the ESYNCR1 EMODE bit Interrupt Request Reference Failure FMPLL Failure Bypass mode with external reference and PLL off Bypass mode with crystal reference an...

Page 575: ...2 x 64 100 x 5 x 42 Round 199 722 200 MODPERIOD x INCSTEP 42 x 200 8400 which is less than 215 MD quantized 42 x 200 x 100 x 5 215 1 x 64 2 00278 In this example the modulation depth error is 0 00278 The FM parameters can only be changed and FM can only be enabled when the PLL is locked Writing to the SYNFMMR while the PLL is unlocked has no effect Furthermore when the PLL loses lock the FM modula...

Page 576: ...ce the FM parameters have already propagated to the analog circuitry Therefore the sequency for programming FM is 1 Poll the LOCK bit until it asserts 2 Program the MODSEL MODPERIOD and INCSTEP fields of the SYNFMMR 3 Poll the BSY bit of the SYNFMMR until it negates 4 Assert the MODEN bit of the SYNFMMR ...

Page 577: ...odule Memory Map The Error Correction Status Module does not include any logic that provides access control Rather this function is supported using the standard access control logic provided by the IPS controller Table 18 1 is a 32 bit view of the ECSM s memory map Table 18 1 ECSM 32 bit Memory Map ECSM Offset Register 0x00 0x0c Reserved 0x20 0x3c Reserved 0x40 Reserved ECC Configuration ECR 0x44 ...

Page 578: ...RESR Platform RAM ECC Master Number Register PREMR Platform RAM ECC Attributes Register PREAT Platform RAM ECC Data Register PREDR The details on the ECC registers are provided in the subsequent sections 18 4 1 1 ECC Configuration Register ECR The ECC Configuration Register is an 8 bit control register for specifying which types of memory errors are reported In all systems with ECC the occurrence ...

Page 579: ...ess and attribute reporting registers 3 Re read the ESR and verify the current contents matches the original contents If the two values are different go back to step 1 and repeat 4 When the values are identical write a 1 to the asserted ESR flag to negate the interrupt request See Figure 18 2 and Table 18 3 for the ECC Status Register definition Register address ECSM Base 0x43 7 6 5 4 3 2 1 0 R 0 ...

Page 580: ... definition Register address ECSM Base 0x47 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 PRNCE PFNCE W RESET 0 0 0 0 0 0 0 0 Unimplemented Table 18 3 ECC Status ESR Field Definitions Name Description Value PRNCE Platform RAM Non Correctable Error 0 No reportable non correctable platform RAM error has been detected 1 A reportable non correctable platform RAM error has been detected The occurrence of a properly en...

Page 581: ... write is ignored See Figure 18 4 and Table 18 5 for the Platform Flash ECC Master Number Register definition Figure 18 4 Platform Flash ECC Master Number PFEMR Register Register address ECSM Base 0x50 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PFEAR W RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PFEAR W RESET Unimplemented Table 18 4 Platform Flash ECC Address PFEAR Field Descriptions Nam...

Page 582: ...register for capturing the data associated with the last properly enabled ECC event in the platform flash memory Depending on the state of the ECC Configuration Register an ECC event in the platform flash causes the address attributes and data associated with the access to be loaded into the PFEAR PFEMR PFEAT and PFEDR registers and the appropriate flag PFNCE in the ECC Status Register to be asser...

Page 583: ...to be asserted This register can only be read from the IPS programming model any attempted write is ignored See Figure 18 7 and Table 18 8 for the Platform RAM ECC Address Register definition Register address ECSM Base 0x58 0x5c 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 R PFEDR W RESET 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 R PFEDR W RESET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 584: ... It was estimated that implementation of a 32 bit RAM ECC provides 7 8 overall performance improvement over a 64 bit organization that would force read modify write cycles to write 32 bit data Each 32 bit word requires a 7 bit ECC code so the RAM array is organized in two banks of 39 bits each In order to support the new 32 bit boundary ECC structure and maintain compatibility with other devices o...

Page 585: ...t organized memories Each 7 bit raw syndrome is formed by 6 bits of Hamming decoded parity plus an odd parity bit for the entire 39 bit 32 bit data 7 ECC code word The upper 6 bits of the raw syndrome specify the exact bit position in error for single bit correctable codewords and the combination of a non zero 6 bit syndrome plus overall incorrect parity bit signal a multi bit non correctable erro...

Page 586: ...0x06 Even 30 0x0A 0x0A Even 29 0x0C 0x0C Even 28 0x0E 0x0E Even 27 0x12 0x12 Even 26 0x14 0x14 Even 25 0x16 0x16 Even 24 0x18 0x18 Even 23 0x1A 0x1A Even 22 0x1C 0x1C Even 21 0x50 0x1E Even 20 0x22 0x22 Even 19 0x24 0x24 Even 18 0x26 0x26 Even 17 0x28 0x28 Even 16 0x2A 0x2A Even 15 0x2C 0x2C Even 14 0x58 0x2E Even 13 0x30 0x30 Even 12 0x32 0x32 Even 11 0x34 0x34 Even 10 0x64 0x36 Even 9 0x38 0x38 ...

Page 587: ...register can only be read from the IPS programming model any attempted write is ignored See Figure 18 9 and Table 18 11 for the Platform RAM ECC Master Number Register definition Figure 18 9 Platform RAM ECC Master Number PREMR Register Even 5 0x42 0x42 Even 4 0x44 0x44 Even 3 0x46 0x46 Even 2 0x48 0x48 Even 1 0x4A 0x4A Even 0 0x4C 0x4C Multi bit Non Correctable errors Odd 0x00 0x00 Odd 0x02 0x02 ...

Page 588: ... event in the platform RAM memory Depending on the state of the ECC Configuration Register an ECC event in the platform RAM causes the address attributes and data associated with the access to be loaded into the PREAR PRESR PREMR PREAT and PREDR registers and the appropriate flag PRNCE in the ECC Status Register to be asserted The data captured on a multi bit non correctable ECC error is undefined...

Page 589: ...62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 R PREDR W RESET 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 R PREDR W RESET 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PREDR W RESET 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PREDR W RESET Unimplemented Table 18 13 Platform RAM ECC Data PREDR Field Descriptions Name Description Value PREDR RAM ECC Data Register This 64 bit register contains the...

Page 590: ...MPC563XM Reference Manual Rev 1 590 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 591: ...d application software timing functions The STM includes a 32 bit up counter and four 32 bit compare channels with a separate interrupt source for each channel The counter is driven by the system clock divided by an 8 bit prescale value 1 to 256 19 2 2 Features The STM has the following features One 32 bit up counter with 8 bit prescaler Four 32 bit compare channels Independent interrupt source fo...

Page 592: ... Control Register 32 R W 0x0004 STM_CNT STM Counter Value 32 R W 0x0008 Reserved 32 R W 0x000C Reserved 32 R W 0x0010 STM_CCR0 STM Channel 0 Control Register 32 R W 0x0014 STM_CIR0 STM Channel 0 Interrupt Register 32 R W 0x0018 STM_CMP0 STM Channel 0 Compare Register 32 R W 0x001C Reserved 32 R W 0x0020 STM_CCR1 STM Channel 1 Control Register 32 R W 0x0024 STM_CIR1 STM Channel 1 Interrupt Register...

Page 593: ...0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CPS 0 0 0 0 0 0 FRZ TEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 1 STM Control Register STM_CR Field Description CPS Counter Prescaler Selects the clock divide value for the prescaler 1 256 0x00 Divide system clock by 1 0x01 Divide system clock by 2 0xFF Divide system clock by 256 FRZ Freeze Allows the timer counter t...

Page 594: ... 28 29 30 31 R CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 2 STM Count Register STM_CNT Field Description CNT Timer count value used as the time base for all channels When enabled the counter increments at the rate of the system clock divided by the prescale value Offset 0x10 0x10 n Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 ...

Page 595: ... 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 4 STM Channel Interrupt Register STM_CIRn Field Description CIF Channel Interrupt Flag The flag and interrupt are cleared by writing a 1 to this bit Writing a 0 has no effect 0 No interrupt request 1 Interrupt request due to a match on the channel Offset 0x18 0x10 n Access Read W...

Page 596: ...the STM_CR TEN bit When enabled in normal mode the counter continuously increments When enabled in debug mode the counter operation is controlled by the STM_CR FRZ bit When the STM_CR FRZ bit is set the counter is stopped in debug mode otherwise it continues to run in debug mode The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary The STM has four identical co...

Page 597: ... and Critical Interrupt inputs of the CPU see the SIU chapter for details The SWT includes an interrupt status bit so the ISR software can determine if the NMI request came from the SWT or the external NMI pin 20 1 2 Reset Assertion The SWT can assert a reset when the watchdog timer expires This reset will cause a system reset equivalent to assertion of the RESET pin Bit 6 of the Reset Status Regi...

Page 598: ... protection Hard and soft configuration lock bits 20 2 3 Modes of Operation The SWT supports three device modes of operation normal debug and stop When the SWT is enabled in normal mode its counter runs continuously In debug mode operation of the counter is controlled by the FRZ bit in the SWT_CR If the FRZ bit is set the counter is stopped in debug mode otherwise it continues to run In stop mode ...

Page 599: ...nd controlling the SWT The reset value of this register is device specific Some devices can be configured to automatically clear the SWT_CR WEN bit during the boot process This register is read only if either the SWT_CR HLK or SWT_CR SLK bits are set Table 20 1 SWT Memory Map Address Offset Register Name Register Description Size bits Access 0x0000 SWT_CR SWT Control Register 32 R W 0x0004 SWT_IR ...

Page 600: ...pseudorandom key values are used to service the watchdog RIA Reset on Invalid Access 0 Invalid access to the SWT generates a bus error 1 Invalid access to the SWT causes a system reset if WEN 1 WND Window Mode 0 Regular mode service sequence can be done at any time 1 Windowed mode the service sequence is only valid when the down counter is less than the value in the SWT_WN register ITR Interrupt T...

Page 601: ... 1 SWT counter is stopped in stop mode FRZ Debug Mode Control Allows the watchdog timer to be stopped when the device enters debug mode 0 SWT counter continues to run in debug mode 1 SWT counter is stopped in debug mode WEN Watchdog Enabled 0 SWT is disabled 1 SWT is enabled Offset 0x0004 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 ...

Page 602: ...es used to reset the watchdog timer Offset 0x008 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 21 22 23 24 25 26 27 28 29 30 31 R WTO W Reset1 1 The reset value of the SWT_TO register is device specific Field Description WTO Watchdog time out period in clock cycles An internal 32 bit down counter is loaded with this value or 0x100 which ever is greater when the service se...

Page 603: ...og and to clear the soft lock bit SWT_CR SLK If the SWT_CR KEY bit is set two pseudorandom key values are written to service the watchdog see Section 20 5 for details Otherwise the sequence 0xA602 followed by 0xB480 is written to the WSC field To clear the soft lock bit SWT_CR SLK the value 0xC520 followed by 0xD928 is written to the WSC field Offset 0x014 Access Read Only 0 1 2 3 4 5 6 7 8 9 10 1...

Page 604: ...clock cycles unless the value is less than 0x100 in which case the time out period is set to 0x100 This time out period is loaded into an internal 32 bit down counter when the SWT is enabled and each time a valid service operation is performed The SWT_CR CSL bit selects which clock system or oscillator is used to drive the down counter The reset value of the SWT_TO register is device specific The ...

Page 605: ...r configuration changes may require up to three system plus seven counter clock cycles If window mode is enabled SWT_CR WND bit is set the service sequence must be performed in the last part of the time out period defined by the window register The window is open when the down counter is less than the value in the SWT_WN register Outside of this window service sequence writes are invalid accesses ...

Page 606: ... Reference Manual Rev 1 606 Freescale Semiconductor Preliminary Subject to Change Without Notice SWT_CR WEN cleared and the value of the SWT_CO read to determine if the internal down counter is working properly ...

Page 607: ...s translation for all internal device resources MMU configuration to boot user application compiled as Classic PowerPC Book E code or as Freescale VLE code Passes control to user application code in the internal flash memory Automatic switch to Serial Boot mode if internal flash is blank or invalid Serial boot by loading user program via CAN bus or eSCI to the internal SRAM User programmable 64 bi...

Page 608: ...0 to 0xFFFF_FFFF The actual code size of the BAM program is less than 4 Kbytes and starts at 0xFFFF_F000 repeating itself down every 4Kilobytes in the BAM address space The CPU starts the BAM program execution at its reset vector from address 0xFFFF_FFFC The BAM exits to the user code at 0xFFFF_FFF8 address The last BAM executed instruction is a BLR The link register is preloaded with the user app...

Page 609: ...STOUT before user code starts First the BAM program configures the e200z335 core MMU to allow access to all device internal resources according to Table 21 2 This MMU setup remains the same for internal Flash boot mode Reset Config MMU for Internal boot Internal boot Y N Search for RCHW Found RCHW Y N Internal flash boot MIDR 15 0 Y N Setup muxed calibration bus Check RCHW Found RCHW Y N Cal Bus b...

Page 610: ...n with the BOOTCFG pin to enable disable the internal flash memory and the Nexus interface The address of the Censorship word is 0x00FF_BDE0 The censorship word consists of two fields censorship control Table 21 2 MMU Configuration for Internal Flash Boot TLB Entry Region Logical Base Address Physical Base Address Size Attributes 0 Peripheral Bridge B1 and BAM 1 This device has only a single perip...

Page 611: ... for whatever reason 21 5 3 Reset Configuration Half Word RCHW The Reset Configuration Half Word defines boot options and has to be programmed by the user to predefined locations in the internal flash or at the beginning of the external flash device The next 32 bit word after the RCHW has to be programmed with a starting address of the user application The BAM program uses this location to fetch t...

Page 612: ...re watchdog timer is enabled after passing control to the user application code 0 Disable core software watchdog timer 1 Software watchdog timer maintains its default state out of reset i e enabled The timeout period is programmed to be 2 5 217 system clocks PS0 Port size Defines the width of the data bus connected to the memory on CS0 After system reset CS0 is changed to a 16 bit port by the BAM ...

Page 613: ...o find a valid RCHW in six predefined locations If a valid RCHW is not found the BAM program proceeds to check of possibility of booting from the calibration bus and or to the serial boot mode 21 5 4 1 Finding Reset Configuration Half Word The BAM searches the internal Flash memory for a valid reset configuration half word RCHW Possible RCHW locations are shown in Table 21 6 16 20 48 16 35 20 16 3...

Page 614: ...ate Detection serial boot mode which allows communication with adaptable speed based on measured input signal The Fixed Baud Rate mode or Baud Rate Detection mode are selected based on the state of the EVTO pin recorded in the SIU_RSR ABR bit If the bit is set the Baud Rate Detection mode is selected if the bit is cleared the Fixed Baud Rate is selected The SIU_RSR ABR bit reflects the inverted st...

Page 615: ...d in CAN 2 0A specification See Table 21 8 for examples of baud rates Only one message buffer 0 is used for all communications The bit timing is configured as shown in Figure 21 6 TXD_A GPIO GPIO GPIO TXD_A Push Pull output with medium slew rate RXD_A GPIO RXD_A Input with pull up and hysteresis GPIO RXD_A Input with pull up and hysteresis Table 21 8 Serial Boot Mode Baud Rate Watchdog Summary Cry...

Page 616: ...Download Protocol The download protocol follows four steps 1 Host sends 64 bit password 2 Host sends start address size of download code in bytes and VLE bit 3 Host sends the application code data 4 The device switches to the loaded code at the start address The communication is done in half duplex manner any transmission from host is followed by the device transmission The host computer should no...

Page 617: ...evice stops responding To get the device out of that state the RESET signal must be asserted If the password check passes the BAM transitions to the next step in the protocol 2 Download start address size of download and VLE bit The next 8 bytes received by the device are considered to contain a 32 bit start address the VLE mode bit and a 31 bit code length see Figure 21 7 Figure 21 7 Start Addres...

Page 618: ...prevent possible ECC errors may be caused by the CPU prefetching 4 Switch to the loaded code The BAM program waits for the last echo message transmission to complete then the active communication controller is disabled Its pins revert to GPIO inputs To provide compatibility with older devices the BAM writes the e200z335 core time base registers TBU and TBL with 0x0 and enables the e200z335 core wa...

Page 619: ...1 5 5 6 CAN Baud Rate Detection The host transmits a zero length message with zero 11 bit ID and the device measures time over 40 bits polling CNRX_A pin for high and low according to the sent data The device does not acknowledge this message The CAN baud rate depends on the number of quanta per bit and serial clock frequency which is defined by a prescaler The CAN baud rate detection routine sele...

Page 620: ...ries to read RCHW from logical address 0x2000_0000 If the valid RCHW is read from that address the BAM program reads user application code start address from logical address 0x2000_0004 parses RCHW sets up watchdogs updates EBI SRAM and Internal Flash MMU entries according the RCHW VLE bit and passes control to the user code The RCHW PS0 bit has to be programmed to 1 since the Calibration Bus does...

Page 621: ...000 16 Mbytes Not guarded Big endian Global PID 2 Calibration EBI 0x2000_0000 0x2000_0000 16 Mbytes Not guarded Big endian Global PID Table 21 12 Calibration Bus EBI Register Settings Register Value Comments EBI_MCR 0x0000_0802 Sets the AD_MUX bit EBI_CAL_BR0 0x2000_0883 Sets the AD_MUX bit 16 bit wide bus burst Inhibit EBI_CAL_OR0 0xFF80_00F0 Set 15 wait states 8 MB SIU_PCR340 for CAL_ADDR 12 15 ...

Page 622: ...MPC563XM Reference Manual Rev 1 622 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 623: ...pported 22 1 2 Device Specific Channel Information 22 1 2 1 Channel Descriptions The channels available on this device are described in Table 22 1 22 1 2 2 Channel Connections Table 22 2 shows the eMIOS channel connections for this device Table 22 1 Channel Descriptions Channel Number Description 1 3 5 6 General purpose input output GPIO Single action input capture SAIC Single action output compar...

Page 624: ...ection Serialized IN Serialized OUT 31 24 NC no no 23 I O primary function no yes 22 16 NC no no 15 Output secondary function no yes 14 Output primary function no yes 13 Output secondary function yes yes 12 Output primary function yes yes 11 8 I O primary function no yes 7 NC no no 6 Output secondary function no yes 5 Output secondary function no yes 4 I O primary function no yes 3 NC no yes 2 I O...

Page 625: ...fect on this device The list of parameterizable registers for each channel group see Section 22 1 2 3 Channel Groups is shown in Table 22 4 CH10 CH11 CH12 CH13 CH14 CH15 CH23 Table 22 4 eMIOS Registers per Channel Functionality Category GPIO SAIC SAOC OPWM IPM IPWM DAOC MCB OPWFMB B1 B2 Counter Channel Small Channel Medium Channel Big Table 22 3 eMIOS Channel Groups continued Channel Number SMALL ...

Page 626: ...ounter clock enable Output disable control Bus A CH 0 EMIOSI 0 EMIOSO 0 ipp_obe_emios_ch 0 see note 1 emios_flag_out 0 Notes 1 Connection between UC n 1 and UC n CH 7 EMIOSI 7 EMIOSO 7 ipp_obe_emios_ch 7 emios_flag_out 7 B A CH 8 EMIOSI 8 EMIOSO 8 ipp_obe_emios_ch 8 emios_flag_out 8 ch 15 EMIOSI 15 EMIOSO 15 ipp_obe_emios_ch 15 emios_flag_out 15 C A CH16 EMIOSI 16 EMIOSO 16 ipp_obe_emios_ch 16 emi...

Page 627: ... specific functions not included in MIOS inheritance 22 2 2 Features The basic features of the eMIOS200 are the following Up to 32 channels chosen among Unified or Dedicated Channels not necessarily numbered in a continuous sequence this document shows a 24 Unified Channels implementation Data registers of either 8 16 24 or 32 bit width this document shows 24 bit wide data registers Counter buses ...

Page 628: ... implemented according to devices requirements If an unimplemented mode is selected the results are unpredictable such as writing a reserved value to MODE 0 6 in Section 22 4 2 8 eMIOS200 UC Control Register EMIOSC n Wheel Speed Channels can be configured to operate in the following modes Disable Wheel Speed These modes are described in Section 22 5 2 Wheel Speed Channel WSC 22 3 External Signal D...

Page 629: ...lag_out n outputs the state of F n bit of EMIOSGFLAG register 22 4 Memory Map Register Definition 22 4 1 Memory Map The overall address map organization is shown in Table 22 6 Whenever an access to either an absent register or absent channel is performed the eMIOS200 responds asserting Transfer Error signal from SkyBlue Line interface as well as for access to reserved address 1 Value 0 refers to t...

Page 630: ...address is used as reference The WS Channel is classified as Dedicated Channel different from the Unified Channel which implements the standard eMIOS200 modes Table 22 8 describes the Wheel Speed Channel memory map 220 31F Channel 16 1 to Channel 23 1 320 FFF reserved 1 It is recommended to allocate Unified Channels at slots 0 8 16 23 24 as these slots drive internal time buses Table 22 7 Unified ...

Page 631: ...S 1 Enable to enter low power mode when Doze Mode is requested 0 Not enable to enter low power mode when Doze Mode is requested MDIS Module Disable bit MDIS Module Disable bit Puts the eMIOS200 in low power mode The MDIS bit is used to stop the clock of the block except the access to registers EMIOSMCR EMIOSOUDIS and EMIOSUCDIS 1 Enter low power mode 0 Clock is running 14 EVENT register EMIOSWSEV ...

Page 632: ...the module and provide a method to start time bases of several blocks simultaneously 1 Global Time Base Enable Out signal asserted 0 Global Time Base Enable Out signal negated NOTE The Global Time Base Enable input pin controls the internal counters When asserted Internal counters are enabled When negated Internal counters disabled ETB External Time Base bit The ETB bit selects the time base sourc...

Page 633: ...te whether at least one of the flags overruns selected by FLAGSEL 0 4 bits see Table 22 22 in EMIOSWSC2 n register is high F n Channel n Flag bit Channels that occupy a pair of slots such as WSC are referred to by their lower slot number LSB 0 standard therefore the bits that correspond to their higher slot number always read 0 Table 22 9 Global Prescaler clock divider GPRE 0 7 Divide ratio 000000...

Page 634: ...ster EMIOSUCDIS CHDIS n Enable Channel n bit The CHDIS n bit is used to disable each of the channels by stopping its respective clock 1 Channel n disabled 0 Channel n enabled 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 OU2 3 OU2 2 OU2 1 OU2 0 OU1 9 OU1 8 OU1 7 OU1 6 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OU1 5 OU1 4 OU1 3 OU1 2 OU1 1 O...

Page 635: ...n the mode of operation internal registers B1 or B2 can be assigned to address EMIOSB n Both B1 and B2 are cleared by reset Table 22 10 summarizes the EMIOSB n writing and reading accesses for all operation modes For more information see Section 22 5 1 1 UC Modes of Operation Depending on the channel configuration it may have EMIOSB register or not EMIOSB register is required for the following mod...

Page 636: ...n Mode Register access write read write read alt write alt read GPIO A1 A2 A1 B1 B2 B1 A2 A2 SAIC1 A2 B2 B2 SAOC1 1 In these modes the register EMIOSB n is not used but B2 can be accessed A2 A1 B2 B2 IPWM A2 B1 IPM A2 B1 DAOC A2 A1 B2 B1 PEA A1 A2 B1 PEC1 A1 A1 B1 B1 A2 QDEC1 A1 A1 B2 B2 WPTA A1 A1 B1 B1 A2 MC1 A2 A1 B2 B2 OPWFM A2 A1 B2 B1 OPWMC A2 A1 B2 B1 OPWM A2 A1 B2 B1 OPWMT A1 A1 B2 B1 A2 A...

Page 637: ... it In this case EMIOSCNT availability should be explicitly described in the device SoC Guide 22 4 2 8 eMIOS200 UC Control Register EMIOSC n EMIOSC n address UC n base address 0C Figure 22 9 eMIOS200 UC Control Register EMIOSC n The Control register gathers bits reflecting the status of the UC input output signals and the overflow condition of the internal counter as well as several read write con...

Page 638: ...l as shown in Table 22 12 UCPREN Prescaler Enable bit The UCPREN bit enables the prescaler counter 1 Prescaler enabled 0 Prescaler disabled no clock 0 1 DMA Direct Memory Access bit The DMA bit selects if the FLAG generation will be used as an interrupt or as a DMA request 1 Flag overrun assigned to DMA request 0 Flag overrun assigned to Interrupt request IF 0 3 Input Filter bits The IF 0 3 bits c...

Page 639: ...ct For input modes the FORCMA bit is not used and writing to it has no effect FORCMB Force Match B bit For output modes the FORCMB bit is equivalent to a successful comparison on comparator B except that the FLAG bit is not set This bit is cleared by reset and is always read as zero This bit is valid for every output operation mode which uses comparator B otherwise it has no effect 1 Force a match...

Page 640: ...al counter or an input capture or a FLAG When not shown in the mode of operation description this bit has no effect 1 Trigger on a rising edge 0 Trigger on a falling edge For QDEC MODE 6 cleared the EDPOL bit selects the count direction according to direction signal UC n input 1 counts up when UC n is asserted 0 counts down when UC n is asserted NOTE UC n 1 EDPOL bit selects which edge clocks the ...

Page 641: ...e_B encoders type 0001110 Windowed Programmable Time Accumulation 0001111 Reserved 001000b Modulus Counter Up counter with clear on match start 001001b Modulus Counter Up counter with clear on match end 00101bb Modulus Counter Up Down counter 00110b0 Output Pulse Width and Frequency Modulation immediate update 00110b1 Output Pulse Width and Frequency Modulation next period update 00111b0 Center Al...

Page 642: ...bit 0 Do not change OVR bit OVFL Overflow bit The OVFL bit indicates that an overflow has occurred in the internal counter OVFL must be cleared by software writing a 1 to the OVFLC bit 1 An overflow had occurred 0 No overflow OVFLC Overflow Clear bit The OVFL bit must be cleared by writing a 1 to the OVFLC 1 Clear OVFL bit 0 Do not change OVFL bit UCIN Unified Channel Input pin bit 1 b adjust para...

Page 643: ...2 11 eMIOS200 UC Alternate A register EMIOSALTA n The EMIOSALTA n register provides an alternate address to access A2 channel registers in restricted modes GPIO PEC WPTA OPWMT only If EMIOSA n register is used along with EMIOSALTA n both A1 and A2 registers can be accessed in these modes Figure 22 10 summarizes the EMIOSALTA n writing and reading accesses for all operation modes Please see Section...

Page 644: ... n EMIOSWSCAPB n address WSC n base address 04 Figure 22 13 eMIOS200 WSC Capture B Register EMIOSWSCAPB n The EMIOSWSCAPB n register is dedicated to access the T24CAPB n register This register is updated with T24CAPB1 n content when the host reads EMIOSWSCAEC n byte enables in EMIOSWSCAEC register accesses are ignored for this purpose T24CAPB1 n stores the time for the previous edge relative to th...

Page 645: ...peration CPREN T16PWCNT Counter Prescaler Enable bit The CPREN bit enables the channel prescaler to be connected to the T16PWCNT counter 1 Prescaler enabled 0 Prescaler disabled no clock DMA Direct Memory Access bit The DMA bit selects if the FLAG generation will be used as an interrupt or as a DMA request It does not affect OVERRUN that is never indicated through DMA 1 FLAGSEL selected flags assi...

Page 646: ...f the counter buses to be used by the Wheel Speed Channel Refer to Table 22 17 for details EDSELCAP Capture Register Edge Selection bit The EDSELCAP bit acts combined with the EDPOLCAP bit to select which edges trigger the following events load T24CAPA with the selected external counter bus value load T24CAPB1 with T24CAPA value increment EVCNT counter clear T16PWCNT counter depending on PWSWR and...

Page 647: ...rol Register 2 EMIOSWSC2 n The EMIOSWSC2 n register provides configuration control bits for the Wheel Speed Channel internal logic Although this register can be written whatever mode WSC is running it is strongly recommended that any change in the content of its fields except for PWSWR and PWREN be done only during Disable mode otherwise the results are unpredictable WSPRE 0 7 Prescaler bits Table...

Page 648: ...6PWCNT reset on a T24CAP event EDSELPW Pulse Width Detection Edge Selection bit The EDSELPW bit acts combined with the EDPOLPW bit to select which edges trigger the capture of the Pulse Width counter See Table 22 21 1 Either both edges or none triggering 0 Either falling or rising edge triggering EDPOLPW Pulse Width Detection Edge Polarity bit The EDPOLPW bit acts combined with the EDSELPW bit to ...

Page 649: ...1 FLAGCE OVRCE 1 The selected FLAG OVERRUN needs to be validated by the FEN bit FLAG enable bit in order to generate either an Interrupt or a DMA request 2 The Flag selection is one hot encoded thus allowing more than one flag to be selected at the same time Since the Flag Overrun can also generate an interrupt the FLAGSEL is also used to select the overrun bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 650: ...AGPWO Clear bit Writing 1 to FLAGPWOC bit clears the FLAGPWO status bit This bit is self negated thus reading it returns always 0 1 Clear FLAGPWO bit 0 No effect FLAGCAPC FLAGCAP Clear bit Writing 1 to FLAGCAPC bit clears the FLAGCAP status bit This bit is self negated thus reading it returns always 0 1 Clear FLAGCAP bit 0 No effect FLAGPWC FLAGPW Clear bit Writing 1 to FLAGPWC bit clears the FLAG...

Page 651: ... Width Detection logic with the FLAGPW already set This flag is cleared if the Status register is written with the OVRPWC bit set 1 FLAGPW Overrun 0 FLAGPW no overrun OVRECO FLAGECO Overrun bit The OVRECO Flag indicates that an overflow occurred in the EVCNT counter with the FLAGECO already set This flag is cleared if the Status register is written with the OVRECOC bit set 1 FLAGECO Overrun 0 FLAG...

Page 652: ... out of freeze state byte enables in EMIOSWSPW register accesses are ignored for this purpose If when attempting to clear the FLAGPW flag a new event occurs at the same time then the flag remains set indicating that a new capture event had occurred 1 Capture event detected 0 Capture event not detected FLAGECO FLAG Event Counter Overflow bit The FLAGECO bit is set when the Event Counter register ov...

Page 653: ...MIOS200 WSC Capture Event Register EMIOSWSCEV n EMIOSWSCEV n address WSC n base address 18 Figure 22 18 eMIOS200 WSC Capture Event Register eMIOSWSCEV n The EMIOSWSCEV n register provides read access to the 24 bit T24CAPEV register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EVENT ...

Page 654: ...or in Disable mode the EMIOSWSPWCNT n register is read write able Otherwise when the channel is in Wheel Speed mode the EMIOSWSPWCNT n is a read only register 22 5 Functional Description The eMIOS200 provides independent channels UC WSC that can be configured and accessed by a host MCU Up to four time bases can be shared by the channels through four counter buses and each channel can generate its ...

Page 655: ...s channels in slots from 16 through 23 Counter bus E drives channels from 24 through 31 Note that the first channel in a 8 channel slice drives the local counter bus for that slice therefore this channel should not be assigned to be driven by the same counter bus otherwise a loop occurs The eMIOS200 Interrupt request signal DMA transfer request signal among others are wired to a specific channel t...

Page 656: ...espective local bus B for the 7 0 slice and D for the 23 16 slice or by the global counter bus A Note that there are unified Channels with no external pin associated to it Those channels are used to trigger internal SoC signals such as Interrupt requests or DMA transfer requests Since channel 31 channel 24 channel 23 channel 16 channel 15 channel 8 channel 7 channel 0 bus E bus D bus C bus B globa...

Page 657: ...l timing functions A programmable clock prescaler Two double buffered data registers A and B that allow up to two input capture and or output compare events to occur before software intervention is needed Two comparators equal only A and B which compares the selected counter bus with the value in the data registers Internal counter which can be used as a local time base or to count input events co...

Page 658: ...rom others modes thus allowing to optimize the logic by disabling the mode and therefore its associated logic The unused gates are removed during the synthesis phase Targeting the logic optimization a set of registers is shared by the modes thus providing sequencial events to be stored The Datapath block provides the channel A and B registers the internal time base and comparators Multiplexors sel...

Page 659: ...pt for GPIO mode the output flip flop is set to disabled state according to ODIS bit in the EMIOSC n register As the internal counter EMIOSCNT n continues to run in all modes except for GPIO mode it is possible to use this as a time base if the resource is not used in the current mode A2 B2 B1 A1 CNT local counter bus global counter bus A A Comparator BSL 0 BSL 1 logic BSL 1 logic BSL 1 logic inte...

Page 660: ...id and unexpected output compare or input capture results or the FLAGs being set incorrectly In GPIO input mode MODE 0 6 0000000 the FLAG generation is determined according to EDPOL and EDSEL bits and the input pin status can be determined by reading the UCIN bit In GPIO output mode MODE 0 6 0000001 the Unified Channel is used as a single output port pin and the value of the EDPOL bit is permanent...

Page 661: ...PIO mode the output flip flop is set to the complement of the EDPOL bit in the EMIOSC n register Counter bus can be either internal or external and is selected through BSL 0 1 bits Figure 22 27 and Figure 22 28 show how the Unified Channel can be used to perform a single output compare with EDPOL value being transferred to the output flip flop and toggling the output flip flop at each match respec...

Page 662: ...ve or negative pulse by capturing the leading edge on register B1 and the trailing edge on register A2 Successive captures are done on consecutive edges of opposite polarity The leading edge sensitivity i e pulse polarity is selected counter bus 000500 001000 001100 001000 001100 001000 output flip flop Update to A1 A1 value1 xxxxxx 001000 FLAG pin register 001000 001000 001000 A1 match A1 match A...

Page 663: ...abled until the next read of EMIOSB n register Reading EMIOSB n register forces B1 be updated with A1 register content and re enables transfers from B2 to B1 to take effect at the next trailing edge capture Transfers from B2 to A1 are not blocked at any time The input pulse width is calculated by subtracting the value in B1 from A2 Figure 22 30 shows how the Unified Channel can be used for input p...

Page 664: ...nt captures the FLAG line is set and data in register B2 is transferred to register B1 When the second edge of the same polarity is detected the counter bus value is latched into registers A2 and B2 the data previously held in register B2 is transferred to data register B1 and to register A1 The FLAG bit is set to indicate the start and end points of a complete period have been captured This seque...

Page 665: ...he variable pulse width output are generated by matches occurring on comparators A and B There is no restriction concerning the order in which A and B matches occur When the DAOC mode is entered coming out from GPIO mode both comparators are disabled and the output flip flop is set to the complement of the EDPOL bit in the EMIOSC n register selected counter bus 000500 001000 001100 001250 001525 0...

Page 666: ... A1 and B1 pulses will continue to be generated regardless of the state of the FLAG bit At any time the FORCMA and FORCMB bits allow the software to force the output flip flop to the level corresponding to a comparison event in comparator A or B respectively Note that the FLAG bit is not affected by these forced operations NOTE If both registers A1 and B1 are loaded with the same value the B match...

Page 667: ...cate that an event has occurred The desired time interval can be determined by subtracting register B1 from A2 Registers EMIOSA n and EMIOSB n return the values in register A2 and B1 respectively selected counter bus 000500 001000 001100 001000 001100 A1 value1 B1 value2 xxxxxx 001100 001100 001100 xxxxxx 001000 001000 001000 output flip flop A1 match B1 match Update to A1 and B1 FLAG pin register...

Page 668: ...of the counter clock input event is done by a rising or falling edge or both edges on the input pin The polarity of the triggering edge is selected by the EDSEL and EDPOL bits in EMIOSC n register For continuos operation mode MODE 6 cleared MODE 0 6 0001000 the counter is cleared on the next input event after a FLAG generation and continues to operate as described above For single shot operation M...

Page 669: ...xxx B2 value5 001000 xxxxxx 001500 000090 000090 007000 001500 007000 001000 FLAG pin register A1 Match 001500 input signal2 001000 A1 events A1 events no events events 000400 Notes 4 EMIOSA n A2 when reading 5 EMIOSB n B1 3 EMIOSA n A1 when writing 2 After input filter 1 Cleared on the first input event after writing to register A1 007000 MODE 6 0 FFFFFF 000000 EMIOSCNT n 1 Time write to A1 selec...

Page 670: ...rantee coherent measurements when reading EMIOSCNT n after the FLAG is set the software must check if the time base value is out of the time interval defined by registers A1 and B1 Alternatively register A2 always holds the latest available measurement providing coherent data at any time after the first FLAG had occurred This register is addressed by the alternate address EMIOSALTA n For single sh...

Page 671: ... must be connected to the direction signal and UC n 1 input pin must be connected to the count signal of the quadrature encoder UC n EDPOL bit selects count direction according to direction signal and UC n 1 EDPOL bit selects if the internal counter is clocked by the rising or falling edge of the count signal When operating with phase_A phase_B encoder MODE 6 set UC n input pin must be connected t...

Page 672: ...start counting The internal counter is used as a time accumulator i e it counts up when the input signal has the same polarity of EDPOL bit in EMIOSC n register and does not count otherwise When a match occurs in comparator B the internal counter is disabled regardless of the input signal polarity and the FLAG bit is set At the same time the content of EMIOSCNT n is transferred to register A2 Read...

Page 673: ...s the value in register A1 Register B1 is cleared and is not accessible to the MCU MODE 4 bit selects up mode or up down mode when cleared or set respectivelly When in up count mode a match between the internal counter and register A1 sets the FLAG and clears the internal counter The timing of those events varies according to the MC mode setup as follows Internal counter clearing on match start MO...

Page 674: ...ar on Match End sub modes When in up down count mode MODE 0 6 00101bb a match between the internal counter and register A1 sets the FLAG and changes the counter direction from increment to decrement A match between register B1 and the internal counter changes the counter direction from decrement to increment and sets the FLAG only if MODE 5 bit is set Only values different than 0 must be written a...

Page 675: ... in the EMIOSC n channel register When entering in MCB mode if up counter is selected by MODE 4 0 MODE 0 6 101000b the internal counter starts counting from its current value to up direction until A1 match occurs The internal counter is set to 1 when its value matches A1 value and a clock tick occurs either prescaled clock or input pin event If up down counter is selected by setting MODE 4 1 the c...

Page 676: ...s set to 1 flags are also generated at the cycle boundary Figure 22 47 Modulus Counter Buffered MCB Up Down Mode Figure 22 48 describes in more detail the A1 register update process in up counter mode The A1 load signal is generated at the last system clock period of a counter cycle Thus A1 is updated with A2 value at the same time that the counter EMIOSCNT n is loaded with 1 The load signal pulse...

Page 677: ...Mode A1 Register Update in Up Down Counter Mode 22 5 1 1 13 Output Pulse Width and Frequency Modulation OPWFM Mode In this mode duty cycle of output signal is the value defined in register A1 plus one and the period is the value defined in register B1 plus one MODE 6 bit controls the transfer from register B2 to B1 which can be done either immediately MODE 6 cleared MODE 0 6 00110b0 providing the ...

Page 678: ...ations If subsequent comparisons occur on comparators A and B the PWFM pulses continue to be output regardless of the state of the FLAG bit In order to achieve 100 duty cycle both registers A1 and B1 must be set to the same value When a simultaneous match occurs on comparators A and B the output flip flop is set to the value of EDPOL bit 0 duty cycle is possible by writing 0 to register A When a m...

Page 679: ...not within that range then the B match will not occur causing the channel internal counter to wrap at the maximum counter value which is ff_ffff for a 24 bit counter After the counter wrap occurs it returns to 1 and resume normal OPWFMB mode operation Thus in order to avoid the counter wrap condition make sure its value is within the 1 to B1 register value range when the OPWFMB mode is entered Whe...

Page 680: ... in this mode the channel internal logic infers a match as if A1 1 with the difference that in this case the posedge of the match signal is used to trigger the output pin transition instead of the negedge used when A1 1 Note that A1 posedge match signal from cycle n 1 occurs at the same time as B1 negedge match signal from cycle n This allows to use the A1 posedge match to mask the B1 negedge matc...

Page 681: ...delay the A1 and B1 registers update for synchronization purposes In Figure 22 54 it is assumed that both the channel and global prescalers are set to 1 each divide ratio is two meaning that the channel internal counter transitions at every four system clock cycles FLAGs can be generated only on B1 matches when MODE 5 is cleared or on both A1 and B1 matches when MODE 5 is set Since B1 flag occurs ...

Page 682: ...se active high signals and a high to low transition at A1 match In this case EDPOL should be set to 0 Note that both the channel and global prescalers are set to 0 each divide ratio is one meaning that the channel internal counter transitions at every system clock cycle EDPOL 0 cycle n cycle n 1 cycle n 2 A1 value1 B1 value B2 value 8 2 6 8 1 internal counter 4 6 MODE 6 1 A2 value1 2 4 6 2 4 6 8 6...

Page 683: ...put flip flop to the level corresponding to a match on comparators A or B respectively Similarly to a B1 match FORCMB sets the internal counter to 1 The FLAG bit is not set by the FORCMA or FORCMB bits being asserted Figure 22 56 describes the generation of 100 and 0 duty cycle signals It is assumed EDPOL 0 and the resultant prescaler value is 1 Initially A1 8 and B1 8 In this case B1 match has pr...

Page 684: ... the output PWM duty cycle is equal to the sum of register A1 and register B1 Mode 6 bit selects between trailing and leading dead time insertion respectively NOTE The internal counter may be running in the internal prescaler ratio while the selected time base may be running in a different prescaler ratio The output signal may produce an unexpected output if the dead time interval is greater than ...

Page 685: ...n freeze state the FORCMA or FORCMB bits only allow the software to force the output flip flop to the level corresponding of a match on A or B respectively If subsequent matches occur on comparators A and B the PWM pulses continue to be generated regardless of the state of the FLAG bit In order to achieve a duty cycle of 100 both registers A1 and B1 must be set to the same value When a simultaneou...

Page 686: ...Notes 1 EMIOSA n A1 2 EMIOSB n B1 Match A1 000303 Match A1 000200 000000 internal counter Time update to B1 000010 Match B1 000010 Match B1 B1 value2 A2 A1according to OU n bit B2 B1according to OU n bit MODE 6 1 000303 000000 selected counter bus Time Match A1 A1 value1 000303 000303 000200 update to A1 update to A1 000200 Match A1 xxxxxx 000200 output flip flop Notes 1 EMIOSA n A1 2 EMIOSB n B1 ...

Page 687: ...sum of register A1 and register B1 Mode 6 bit selects between trailing and leading dead time insertion respectively NOTE The internal counter runs in the internal prescaler ratio while the selected time base may be running in a different prescaler ratio When OPWMCB mode is entered coming out from GPIO mode the output flip flop is set to the complement of the EDPOL bit in the EMIOSC n register The ...

Page 688: ... is set to the value of the EDPOL bit In the following match between register A1 and the selected time base the output flip flop is set to the complement of the EDPOL bit This sequence repeats continuously The internal counter should not reach 0 as consequence of a rollover In order to avoid it the user should not write to EMIOSB register a value greater than twice the difference between external ...

Page 689: ...ween register A1 and the selected time base the internal counter is set to 1 and B1 matches are enabled When the match between register B1 and the selected time base occurs the output flip flop is set to the complement of the EDPOL bit This sequence repeats continuously EDPOL 1 internal time base internal counter is set to 1 on A1 match dead time A1 value A2 value B1 value B2 value write to B2 sel...

Page 690: ...d time insertion FORCMA force a transition in the output flip flop to the opposite of EDPOL In trail dead time insertion the output flip flop is forced to the value of EDPOL bit If FORCMB bit is set the output flip flop value depends upon the selected dead time insertion mode In lead dead time insertion FORCMB forces the output flip flop to transition to EDPOL bit value In trail dead time insertio...

Page 691: ...alue In case of 100 duty cycle the transition from EDPOL to the opposite of EDPOL may be obtained by forcing pin using FORCMA and or FORCMB NOTE If A1 is set to 1 at OPWMCB entry the 100 duty cycle may not be obtained in the very first PWM cycle due to the pin condition at mode entry Only values different than 0 are allowed to be written to A1 register If 0 is loaded to A1 the results are unpredic...

Page 692: ...OPWMCB mode is similar to OPWFMB regarding matches and output pin transition 22 5 1 1 17 Output Pulse Width Modulation OPWM Mode Registers A1 and B1 define the leading and trailing edges of the PWM output pulse respectively MODE 6 bit controls the transfer from register B2 to B1 which can be done either immediately MODE 6 cleared MODE 0 6 01000b0 providing the fastest change in the duty cycle or a...

Page 693: ...le by writing 0 to register A When a match occurs the output flip flop is set at every period to the complement of EDPOL bit The transfer from register B2 to B1 is still controlled by MODE 6 bit NOTE If A1 and B1 are set to the 0 a 0 duty cycle waveform is produced Figure 22 63 and Figure 22 64 show the Unified Channel running in OPWM with immediate update and next period update respectivelly Figu...

Page 694: ...mparators A and B the PWM pulses continue to be generated regardless of the state of the FLAG bit FORCMA and FORCMB bits allow the software to force the output flip flop to the level corresponding to a match on A1 or B1 respectively FLAG bit is not set by the FORCMA and FORCMB operations At OPWMB mode entry the output flip flop is set to the value of the EDPOL bit in the EMIOSC n register Followin...

Page 695: ... instead of the negedge to transition the output flip flop Figure 22 66 describes the channel operation for 0 duty cycle Note that the A1 match posedge signal occurs at the same time as the B1 8 negedge signal In this case A1 match has precedence over B1 match causing the output pin to remain at EDPOL bit value thus generating a 0 duty cycle signal 1 4 match A1 negedge detection 6 A1 value 000004 ...

Page 696: ... the following A1 or B1 match Note that the Output Disable does not modify the Flag bit behavior Note that there is one system clock delay between the assertion of the output disable signal and the transition of the output pin to EDPOL 1 4 match A1 negedge detection 8 A1 value 000004 A1 match A1 match negedge detection output pin EDPOL 0 Selected TIME match B1 negedge detection B1 match B1 match n...

Page 697: ...on with Trigger OPWMT Mode OPWMT mode MODE 0 6 0100110 is intended to support the generation of Pulse Width Modulation signals where the period is not modified while the signal is being output but where the duty cycle will be varied and must not create glitches The mode is intended to be used in conjunction with other channels EDPOL 0 cycle n cycle n 1 cycle n 2 A1 value B1 value B2 value 000008 0...

Page 698: ...tput pulse and as such the duty cycle of the PWM signal To synchronize B1 update with the PWM signal and so ensure a correct output pulse generation the transfer from B2 to B1 is done at every match of register A1 This behavior is the same as the OPWM mode with next period update EMIOSOUDIS register affects transfers between B2 and B1 only In order to account for the shift in the leading edge of t...

Page 699: ... to be generated regardless of the state of the FLAG bit At OPWMT mode entry the output flip flop is set to the complement of the EDPOL bit in the EMIOSC n register In order to achieve 0 duty cycle both registers A1 and B must be set to the same value When a simultaneous match on comparators A and B occur the output flip flop is set at every period to the complement value of EDPOL In order to achi...

Page 700: ...Time output flip flop A1 value1 write to B2 000400 B1 value B2 value2 000700 Match B1 write to A1 xxxxxx 000400 001000 000700 and B2 001000 Match A1 Match B1 Match A1 Notes 1 EMIOSA n A1 2 EMIOSB n B2 for write B1 for read 000700 Notes A2 value 000500 000500 FLAG pin register Match A2 Match A2 0011FF 001000 000000 selected counter bus Time output flip flop A1 value1 write to B2 000400 B1 value B2 ...

Page 701: ...crementing If a counter overflows occurs the new pin value is validated In this case it is transmitted as a pulse edge to the edge detector If the opposite edge appears on the pin before validation overflow the counter is reset At the next pin transition the counter starts counting again Any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed ...

Page 702: ... the desired value for prescaling rate at UCPRE 0 1 bits in EMIOSC n register 3 Enable channel prescaler by writing 1 at UCPREN bit in EMIOSC n register 4 Enable global prescaler by writing 1 at GPREN bit in EMIOSMCR register The prescaler is not disabled during either freeze state or negated GTBE input 22 5 1 4 Effect of Freeze on the Unified Channel When in debug mode FRZ bit in the EMIOSMCR reg...

Page 703: ...23 and T24CAPB 0 23 is not guaranteed does not exist 22 5 2 1 2 Wheel Speed Mode In Wheel Speed mode the Wheel Speed Channel is able to provide data for instantaneous and average wheel speed measurement It also provides high time or low time pulse width measurement on the sensor input signal A periodic interrupt to the CPU is generated thus allowing periodic checking of the channel timing register...

Page 704: ...T24CAPA is controlled by a software loop routine which can be asynchronous to the channel operation or triggered by an interrupt generated by the channel This interrupt can be based on a match between the EVCNT counter register and the EVENT register or on an event detection Edge T24 CAP A T24 CAP B1 T24 CAP B EVENT EVCNT T24 CAP EV T16PW CAP T16PW CNT L En L L L R CPU reads Input pin skyblue read...

Page 705: ...or read providing coherent data if T24CAPA is read before T24CAPB in Wheel Speed mode out of freeze Also T24CAPA and EVCNT are coherent since they are accessed at the same 32 bit read access Figure 22 76 describes the wheel speed measurement for rising edge sensor In this case the T24CAPA register is only triggered on the rising edges of the sensor output signal This type of sensor uses the pulse ...

Page 706: ...e width measurement Programmable interrupt generation periodic or on input signal events1 Input event counting Sensor signal edge slope selection independently for edge capture and pulse width measurement 22 5 2 2 Wheel Speed Channel System Level Architecture From a system level perspective the WS channels can be interconnected the same way as the Unified Channels Thus allowing for the channels to...

Page 707: ...the Status Register indicate when events from several sources had occurred In order to clear a flag one has some alternatives write to the correspondent Flag Clear bit see Figure 22 16 access the appropriate register EMIOSWSCAEC n EMIOSWSEV n EMIOSWSPW n that clears the one flag see Section 22 4 2 15 eMIOS200 WSC Status Register EMIOSWSS n description which requires special care from software appl...

Page 708: ...Table 22 24 simultaneous clear FLAG event occurs row D of Table 22 24 That behavior is summarized in Table 22 24 Below are pictured some examples of the flag flag overrun and respective clear signals behavior Figure 22 78 describes the general behavior of a flag set event followed by a flag clear event In this case the flag overrun bit is not shown since this bit remains cleared Figure 22 78 FLAG ...

Page 709: ...current to a flag clear event In this case the flag remains set and the flag overrun is not set A second flag clear is needed in order to finally clear the flag Figure 22 80 Concurrent FLAG Set and Clear 22 5 2 4 Wheel Speed Channel Programmable Input Filter The input filter for WSC is identical to the UC filter Please refer to Section 22 5 1 2 Input Programmable Filter IPF The corresponding table...

Page 710: ...Wheel Speed Channel Freeze state is entered when FRZ and FREN control bits are set and ipg_debug signal is asserted The only difference on behavior of Wheel Speed Channel between Freeze state and Disable mode sits in the Freeze state entry both T16PWCNT 0 15 and EVCNT 0 7 counters are stopped but not cleared Once Freeze state has been entered the behavior of Wheel Speed Channel in similar to that ...

Page 711: ...nd the module is in debug mode the operation of REDC submodule is not affected i e there is no freeze function in this submodule 22 5 5 Global Clock Prescaler Submodule GCP The GCP divides the system clock to generate a clock for the CPs of the channels The main clock signal is prescaled by the value defined in Table 22 9 according to the GPRE 0 7 bits in EMIOSMCR register The global prescaler is ...

Page 712: ...the contents of EMIOSA n or EMIOSB n were not updated with the correct value before the time base matches the previous contents of EMIOSA n or EMIOSB n When interrupts are enabled the software must clear the FLAG bits before exiting the interrupt service routine 22 6 2 Application Information Correlated output signals can be generated by all output operation modes Bits OU n of EMIOSOUDIS register ...

Page 713: ...cted the internal counter behaves as described in Figure 22 85 If MC mode and Clear on Match End are selected the internal counter behaves as described in Figure 22 86 If OPWFM mode is selected the internal counter behaves as described in Figure 22 85 The internal counter clears at the start of the match signal skips the next prescaled clock edge and then increments in the subsequent prescaled clo...

Page 714: ...nable 1 2 the counter will start counting 1 2 3 0 FLAG set event FLAG clear FLAG pin register system clock prescaler clock enable internal counter match value 3 0 1 3 0 2 0 3 0 PRESCALED CLOCK RATIO 3 see note 1 Note 1 When a match occurs the first clock cycle is used to clear the internal counter and only after a second edge of pre scaled clock 1 2 the counter will start counting FLAG set event F...

Page 715: ...llowing basic steps summarize basic output mode startup assuming the channels are initially in GPIO mode 1 global Disable Global Prescaler 2 timebase channel Disable Channel Prescaler 3 timebase channel Write initial value at internal counter 4 timebase channel Set A B register 5 timebase channel Set channel to MC B Up mode 6 timebase channel Set prescaler ratio 7 timebase channel Enable Channel P...

Page 716: ...MPC563XM Reference Manual Rev 1 716 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 717: ...stem perspective high resolution timing is limited by Host CPU overhead required for servicing timing tasks such as period measurement pulse measurement pulse width modulated waveform generation etc On the eTPU high resolution timing is achieved by three main capabilities Reduced latency pin actions are immediate Reduce or eliminate host interrupt service time Double action channel capability redu...

Page 718: ...ime Bases Each eTPU Engine has its own microprocessor and dedicated hardware for processing signals on I O pins and can also interface with external time bases through the Red Line Bus Both eTPU Engine CPUs hereafter called microengines fetch microinstructions from a Shared Code Memory SCM Shared Parameter RAM SPRAM holds eTPU application parameters and work data It is accessed by Host and both mi...

Page 719: ...nction routines reside in SCM which may contain several Functions A Function may be assigned to several Channels but a Channel can be associated with just one Function at a given moment The association between Functions and Channels is defined by Host CPU and is explained in detail in Section 23 4 1 Functions and Threads eTPU hardware supplies resource sharing features that support concurrency a h...

Page 720: ...of TCR1 and TCR2 clock can be independently derived from the system clock or from an external input via the TCRCLK clock pin In addition the TCR2 timebase can be derived from special angle clock hardware which enables implementing angle based functions This feature is added to support advanced angle based engine control applications TCR1 TCR2 MICROENGINE CODE IPI HOST INTERFACE CHANNEL CONTROL TIM...

Page 721: ...ilable Each channel can use any time base or angle counter for either match or capture operation For example a match on TCR1 can capture the value of TCR2 The channels can request service from the microengine due to recognized pin transitions input events or timebase matches The eTPU channels also support the basic single action operations found on TPU3 functionality with the exception that time r...

Page 722: ... i e the most significant bit of the word s 2nd most significant byte is copied in all 8 bits of the most significant read byte Each eTPU channel can be associated with a variable number of parameters located in the SPRAM according to its selected Function In addition the SPRAM can be fully shared between two eTPU Engines enabling direct communication between them High flexibility of the SPRAM uti...

Page 723: ...ree of these operations with unconflicting resources to be executed in parallel in the same microcycle Microengine has also an independent Multiply Divide MAC unit that performs these complex operations in parallel with other microengine instructions Channel functionality is tightly integrated to the instruction set through Channel Control operations and conditional Branch operations which support...

Page 724: ...eplaced by system clock divided by 8 both time bases can be exported or imported via Red Line Shared Time and Counter bus second time base counter can work as an Angle counter enabling angle based applications to match angle instead of time second time base can also be used as a pulse accumulator gated by external signal Event Triggered VLIW processor microengine 2 stage pipeline implementation fe...

Page 725: ...g and ensures servicing all channels by preventing permanent blockage SPRAM shared between Host CPU and both eTPU Engines supporting communication either between Channels and Host or inter channel hardware implementation of 4 Semaphores supports resource sharing between both eTPU Engines Hardware semaphores directly supported by the microengine instruction set dual parameter coherency hardware sup...

Page 726: ...e and Counter bus The IPI Red Line definition is used for sharing real time data between multiple peripherals Contains angle clock hardware supported by microcode which can provide a 24 bit angle bus instead of time bus This feature enables the eTPU to run angle based engine control applications More interrupt types Each eTPU channel can generate a data transfer request interrupt in addition to re...

Page 727: ...condition PRSS tells the pin state at the time when a channel match or transition service request occurred MRLE1 2 can now be negated independently by microcode New Engine Relative address mode allows a function to access SDM addresss space common to one engine but distinct between engines All changes above are upward compatible with the classic eTPU so that legacy object code both Host and microc...

Page 728: ...r programmability is only possible with a RAM SCM On chips where the SCM is implemented as a RAM it can either be accessed directly from IP Bus for code loading or for software breakpoint setting On chips with a ROM SCM an internal SCM Emulation RAM may be used depending on the specific MCU implementation to replace ROM SCM for test or debug purposes SCM Emulation RAM is selected in a MCU specific...

Page 729: ...ime Bases and Section 23 4 7 EAC eTPU Angle Counter for proper use of this signal Table 23 1 eTPU Signal Properties Name Direction Function Reset State Pull up ipp_ind_etpuch_1 0 to ipp_ind_etpuch_1 31 Input eTPU Engine 1 channel signals MCU dependent ipp_do_etpuch_1 0 to ipp_do_etpuch_1 31 Output eTPU Engine 1 channel signals 0 Hi Z1 1 Value 0 refers to the reset value of the signal Hi Z refers t...

Page 730: ... of the two transition events are configured independently by microcode For further information refer to Section 23 4 5 Enhanced Channels and Section 23 4 9 3 3 Transition Detection and Pin Action Control Each channel input signal has an associated synchronizer made of two flip flops sampling the signal on every other system clock2 followed by a digital filter This digital filter can work in three...

Page 731: ... to force the outputs of a group of 8 channels to an inactive level When an ODIS input is active all the channels in its group of 8 that have their bits ODIS 1 in ETPUCxCR register have their outputs forced to the opposite of the value specified in bit OPOL of the same register Therefore channels can be individually selected to be affected by the output disable signals as well as their disabling f...

Page 732: ...gine Registers 0x70 0x7F eTPU 2 Extra Engine Registers 0x80 0x1FF RESERVED1 0x200 0x2FF eTPU 1 2 Global Channel Registers 0x300 0x3FF RESERVED1 0x400 0x7FF eTPU 1 Channel Registers 0x800 0xBFF eTPU 2 Channel Registers 0xC00 0x7FFF RESERVED1 0x8000 0xBFFF2 2 Actual sizes of SCM and SPRAM are MCU dependent SPRAM 0xC000 0xFFFF2 SPRAM PSE mirror 3 3 Parameter Sign Extension access area see Section 23 ...

Page 733: ... 0x5C RESERVED 0x60 ETPUWDTR_1 eTPU 1 Watchdog Timer Register 0x64 RESERVED 0x68 ETPUIDLER_1 eTPU 1 Idle Counter Register 0x6C RESERVED 0x70 ETPUWDTR_2 eTPU 2 Watchdog Timer Register 0x74 RESERVED 0x78 ETPUIDLER_2 eTPU 2 Idle Counter Register 0x7C RESERVED 0x80 0x1FF RESERVED 0x200 ETPUCISR_1 eTPU 1 Channel Interrupt Status Register 0x204 ETPUCISR_2 eTPU 2 Channel Interrupt Status Register 0x208 R...

Page 734: ...ERVED 0x290 ETPUCSSR_1 eTPU 1 Channel Service Status Register 0x294 ETPUCSSR_2 eTPU 2 Channel Service Status Register 0x298 RESERVED 0x29C RESERVED 0x300 0x3FF RESERVED 0x400 ETPUC0CR_1 eTPU 1 Channel 0 Configuration Register 0x404 ETPUC0SCR_1 eTPU 1 Channel 0 Status and Control Register 0x408 ETPUC0HSRR_1 eTPU 1 Channel 0 Host Service Request Register 0x40C RESERVED 0x410 ETPUC1CR_1 eTPU 1 Channe...

Page 735: ...r 0x9F4 ETPUC31SCR_2 eTPU 2 Channel 31 Status and Control Register 0x9F8 ETPUC31HSRR_2 eTPU 2 Channel 31 Host Service Request Register 0x9FC 0x7FFF RESERVED 0x8000 0xBFFF2 Shared Parameter RAM SPRAM 0xC000 0xFFFF2 Shared Parameter RAM SPRAM PSE mirror 3 0x10000 1FFFF4 Shared Code Memory SCM5 1 This register is not implemented in some MCUs see Section 23 3 2 4 ETPUSCMOFFDATAR eTPU SCM Off range Dat...

Page 736: ...SDM read error WDTO1 2 Watchdog Timeout Flags WDTO1 and WDTO2 indicate that a Watchdog Timeout occurred in the respective engine generating a Global Exception These bits are cleared by writing 1 to GEC 1 Global Exception requested by Watchdog timeout 0 No Global Exception pending because of Watchdog timeout MGE1 2 Microcode Global Exception Engine 1 2 These bits indicate that a Global Exception wa...

Page 737: ...ince the last time SCMMISC was cleared SCMMISF SCM MISC Flag The SCMMISF bit is set by the SCM MISC Multiple Input Signature Calculator logic to indicate that the calculated signature does not match the expected value at the end of a MISC iteration See Section 23 4 10 Test and Development Support for more details 1 MISC has read entire SCM array and the expected signature in ETPUMISCCMPR does not ...

Page 738: ...un NOTE Global Time Base Enable action may also depend on other blocks as explained in Section 23 4 6 4 GTBE Global Time Base Enable NOTE When GTBE is turned off with Angle Mode enabled the EAC must be reinitialized before GTBE is turned on again The EAC reinitialization procedure is described in Section 23 4 7 11 Restarting Angle Logic 23 3 2 2 ETPUCDCR eTPU Coherent Dual Parameter Controller Reg...

Page 739: ...ute word address of the first parameter in the buffer is PBBASE 2 PWIDTH Parameter Width Selection This bit selects the width of the parameters to be transferred between the PB and the target address 1 Transfer 32 bit parameters All 32 bits of the parameters are written in the destination address 0 Transfer 24 bit parameters The upper byte remains unchanged in the destination address WR Read Write...

Page 740: ...is accessed at non implemented addresses either by the Host or by the microengine This register can be written by the host with the 32 bit instruction to be executed by the microengine to recover from runaway code This register is global to both eTPU Engines The reset value is MCU dependent For more detail see Section 23 4 2 6 3 SCM Off range Data NOTE This register is not implemented in some of t...

Page 741: ... SoC level and is usually 0xf3775ffb an instruction that clears MRLEs MRLs and TDLs disables channel service requests ends the thread and generates an illegal instruction Global Exception 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ETPUSCMOFFDATA 15 0 W RESET etpu_scm_off_range_data_plug 15 0 Unimplemented or Reserved eTPU 1 Base 0x014 eTPU 2 Base 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 742: ... runs Stop completes on the next system clock after the stop condition is valid The MDIS bit is write protected when VIS 1 NOTE Once MDIS is switched from 1 to 0 or vice versa it must not be written a different value until STF changes accordingly STF Stop Flag Bit Each Engine asserts its stop flag STF to indicate that it has stopped Only then the host can assume that the Engine has actually stoppe...

Page 743: ...put signals and TCRCLK input as shown in Table 23 5 Filtering can be controlled independently by Engine but all input digital filters in the same Engine have same clock prescaling For more details see Section 23 4 5 6 4 Filter Clock Prescaler A new value written to FPSCK only becomes effective when the filter prescaler finishes the current count CDFC 1 0 Channel Digital Filter Control These bits s...

Page 744: ... Digital Filter Control CDFC Selected Digital Filter 00 TPU2 3 Two Sample Mode Using the filter clock which is the system clock divided by 2 4 8 256 as a sampling clock selected by FPSCK field in ETPUECR comparing two consecutive samples which agree with each other sets the input signal state This is the default reset state 01 bypass filter 10 eTPU Three Sample Mode Similar to the TPU2 3 two sampl...

Page 745: ...lock divided by 8 TCR2CTL also determines the TCRCLK edge selected for angle tooth detection in angle mode See Table 23 8 eTPU 1 Base 0x020 eTPU 2 Base 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R TCR2CTL TCRCF AM 0 0 0 TCR2P W RESET 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TCR1CTL TCR1 CS 0 0 0 0 0 TCR1P W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplement...

Page 746: ...led by AM and neither TCR1 nor TCR2 are Red Line Clients the EAC eTPU Angle Clock hardware provides angle information to the channels using the TCR2 bus When AM is reset non angle mode the EAC operation is disabled and its internal registers can be used as general purpose For more information see Section 23 4 7 EAC eTPU Angle Counter 110 do not use with AM 0 no edge1 111 TCR2 frozen except as Red ...

Page 747: ...t determines together with TCR1CS the clock source for TCR1 TCR1 can count on detected rising edge of the TCRCLK signal a Peripheral Timebase source system clock or the system clock divided by 2 see Table 23 11 After reset TCRCLK signal is selected TCR1CS TCR1 Clock Source TCR1CS provides the option to double the TCR1 incrementing speed using system clock as its clock source instead of system cloc...

Page 748: ...y the TCR1 counter or imported from Red Line bus depending on the configuration set in ETPUREDCR Figure 23 9 ETPUTB1R Register TCR1 23 0 TCR1 value TCR1 value used on matches and captures See Section 23 4 6 Time Bases 23 3 3 3 ETPUTB2R eTPU Time Base 2 TCR2 Visibility Register This register provides visibility of the TCR2 time base for host read access see Section 23 4 6 Time Bases This register i...

Page 749: ... 1 2 is enabled 0 Server Client Operation for resource 1 2 is disabled RSC1 2 TCR1 2 Resource Server Client Assignment Bits eTPU 1 Base 0x028 eTPU 2 Base 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 TCR2 23 7 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TCR2 8 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved eTPU 1 Ba...

Page 750: ...EN2 1 RSC2 0 the eTPU Angle Clock hardware cannot be used NOTE RSC1 2 must not be changed when the respective REN1 2 bit is asserted SERVER_ID1 2 Red Line Server Ids 1 2 Red Line Server Ids read only plug values used for TCR1 and TCR2 respectively when Red Line servers SRV1 2 TCR1 2 Resource Server These bits select the address of the specific Red Line Server to which the local TCR1 or TCR2 listen...

Page 751: ... length mode before the current running thread is forced to end For more information on Watchdog operation see Section 23 4 1 4 Watchdog NOTE The TST microcycles are also counted by the watchdog 23 3 4 2 ETPUIDLER eTPU Idle Register This register counts the microcycles in which the microengine is idle see Section 23 4 10 4 1 Idle Counter eTPU 1 Base 0x060 eTPU 2 Base 0x070 31 30 29 28 27 26 25 24 ...

Page 752: ...nel Registers Layout The channel registers area is shown in Figure 23 14 and detailed in next sections for eTPU systems of 32 channels per Engine Reserved areas are placed to allow doubling the number of channels to 64 for each eTPU Engine Figure 23 14 Channel Registers Area eTPU 1 Base 0x068 eTPU 2 Base 0x078 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R IDLE_CNT 31 16 W RESET 0 0 0 0 0 0 0 0...

Page 753: ...tus bit Figure 23 15 ETPUCISR Register CISx Channel x Interrupt Status 1 indicates that channel x has a pending interrupt to the Host CPU 0 indicates that channel x has no pending interrupt to the Host CPU CICx Channel x Interrupt Clear 1 clear interrupt status bit 0 keep interrupt status bit unaltered For details about interrupts see Section 23 4 9 3 10 Channel Interrupt and Data Transfer Request...

Page 754: ... that channel x has no pending data transfer request DTRCx Channel x Data Transfer Request Clear 1 clear status bit 0 keep status bit unaltered For details about interrupts see Section 23 4 9 3 10 Channel Interrupt and Data Transfer Requests eTPU 1 Base 0x210 eTPU 2 Base 0x214 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R DTRS 31 DTRS 30 DTRS 29 DTRS 28 DTRS 27 DTRS 26 DTRS 25 DTRS 24 DTRS 23 ...

Page 755: ...Channel x Interrupt Overflow Clear 1 clear status bit 0 keep status bit unaltered For details about interrupt overflow see Section 23 4 2 2 2 Interrupt and Data Transfer Request Overflow eTPU 1 Base 0x220 eTPU 2 Base 0x224 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R CIOS 31 CIOS 30 CIOS 29 CIOS 28 CIOS 27 CIOS 26 CIOS 25 CIOS 24 CIOS 23 CIOS 22 CIOS 21 CIOS 20 CIOS 19 CIOS 18 CIOS 17 CIOS 16...

Page 756: ...lear 1 clear status bit 0 keep status bit unaltered For details about data transfer request overflow see Section 23 4 2 2 2 Interrupt and Data Transfer Request Overflow eTPU 1 Base 0x230 eTPU 2 Base 0x234 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R DTR OS 31 DTR OS 30 DTR OS 29 DTR OS 28 DTR OS 27 DTR OS 26 DTR OS 25 DTR OS 24 DTR OS 23 DTR OS 22 DTR OS 21 DTR OS 20 DTR OS 19 DTR OS 18 DTR O...

Page 757: ...rored from the Channel Configuration registers see Section 23 3 7 1 ETPUCxCR eTPU Channel x Configuration Register Figure 23 20 ETPUCDTRER Register eTPU 1 Base 0x240 eTPU 2 Base 0x244 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R CIE 31 CIE 30 CIE 29 CIE 28 CIE 27 CIE 26 CIE 25 CIE 24 CIE 23 CIE 22 CIE 21 CIE 20 CIE 19 CIE 18 CIE 17 CIE 16 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11...

Page 758: ...g Status Clear 1 clear watchdog status bit 0 keep watchdog status bit unaltered For details about Watchdog mechanism see Section 23 4 1 4 Watchdog eTPU 1 Base 0x260 eTPU 2 Base 0x264 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R WDS 31 WDS 30 WDS 29 WDS 28 WDS 27 WDS 26 WDS 25 WDS 24 WDS 23 WDS 22 WDS 21 WDS 20 WDS 19 WDS 18 WDS 17 WDS 16 W WDS C 31 WDS C 30 WDS C 29 WDS C 28 WDS C 27 WDS C 26...

Page 759: ...writing HSR 0 in register ETPUCxHSRR of a channel and its respective bit being asserted in ETPUCPSSR 23 3 6 9 ETPUCSSR eTPU Channel Service Status Register ETPUCSSR holds the current channel service status on whether it is being serviced or not see Section 23 4 1 Functions and Threads Only one bit may be asserted in this register at a given time When no channel is being serviced the register read ...

Page 760: ... This organization eases individual channel management NOTE A bus error is issued on read or write accesses to these registers when ETPUECR bit MDIS 1 Writes are ineffective on bus error eTPU 1 Base 0x290 eTPU 2 Base 0x294 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SS31 SS30 SS29 SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 SS19 SS18 SS17 SS16 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 1...

Page 761: ...annel_Base channel_number 0x10 where ETPU_Engine_Channel_Base ETPU_Base 0x400 for Engine 1 ETPU_Engine_Channel_Base ETPU_Base 0x800 for Engine 2 Table 23 14 Channel Registers Map Offset Registers Structure 0x400 eTPU 1 Channel 0 Registers Structure 0x410 eTPU 1 Channel 1 Registers Structure 0x420 eTPU 1 Channel 2 Registers Structure 0x430 0x5E0 eTPU 1 Channel 30 Registers Structure 0x5F0 eTPU 1 Ch...

Page 762: ...ts DTRE Channel Data Transfer Request Enable this bit is mirrored from ETPUCDTRER see Section 23 3 6 6 ETPUCDTRER eTPU Channel Data Transfer Request Enable Register 1 Enable data transfer request for this channel 0 Disable data transfer request for this channel See Section 23 4 9 3 10 Channel Interrupt and Data Transfer Requests CPR 1 0 Channel Priority This field defines the priority level for th...

Page 763: ...ee Section 23 4 1 Functions and Threads The Function assigned to the channel has to be compatible with the channel condition encoding scheme selected by field ETCS ODIS Output Disable This bit enables the channel to have its output forced to the value opposite to OPOL when the output disable input signal corresponding to the channel group that it belongs is active See Section 23 2 2 4 ipp_ind_etpu...

Page 764: ... are mirrored in ETPUCISR see Section 23 3 6 1 ETPUCISR eTPU Channel Interrupt Status Register See also Section 23 4 9 3 10 Channel Interrupt and Data Transfer Requests CIOS Channel Interrupt Overflow Status 1 interrupt overflow asserted for this channel 0 interrupt overflow negated for this channel CIOC Channel Interrupt Overflow Clear 1 clear status bit 0 keep status bit unaltered These bits are...

Page 765: ...23 4 2 2 2 Interrupt and Data Transfer Request Overflow IPS Channel Input Pin State This bit shows the current value of the filtered channel input signal state OPS Channel Output Pin State This bit shows the current value driven in the channel output signal including the effect of the external output disable feature see Section 23 2 2 4 ipp_ind_etpu_odis_ 1 2 0 3 eTPU Channel Output Disable Signal...

Page 766: ...nctional Description 23 4 1 Functions and Threads eTPU processing is event driven in the sense that eTPU microcode only runs to service a request from an event Service Requests may result from the occurrence of any of the following events Host CPU writing a non zero value to the channel HSR Host Service Request field in ETPUCxHSR register occurrence of a time base match an input signal transition ...

Page 767: ...tput from a given channel Once a Thread begins its execution cannot be interrupted A Thread normally finishes when an END microinstruction is executed A given Thread is selected and called by the Scheduler depending on the following the type of event that generated the service request the Function assigned to the target channel target channel pin state the state of the channel logic the priority a...

Page 768: ...e used for microcode so this organization extends the microcode continuous area to the unused area of the Entry Table For this purpose Function numbers should be selected from 0 up to 31 If for example only 8 functions are implemented only the Entry Table locations for Functions 0 to 7 are used and the Entry Table locations for functions 8 to 31 can be used as microinstruction memory adding extra ...

Page 769: ...le match in various modes of match recognition see Section 23 4 5 2 Match Recognition 2 Transition Detect Service Request channel input signal transition detection of a selected edge The eTPU channels support single and double transition which together with the double match options provide various modes of transition detection see Section 23 4 5 3 Transition Detection and Time Base Capture 3 Chann...

Page 770: ... 5 4 Channel Modes If the channel is used for output only there are no transition detections so the Match2 Trans1 column represents only Match2 and Match1 Trans2 column the Match1 In this case Match1 and Match2 are separated to give better state resolution in double match output functions For more information about channel requests refer to Section 23 4 5 Enhanced Channels Besides those events the...

Page 771: ...h 1 Trans 2 Match 2 Trans 1 In Output Pin State1 Channel Flag1 Channel Flag0 0 00000 001 x x x 0 x 0 1 00001 001 x x x 0 x 1 2 00010 001 x x x 1 x 0 3 00011 001 x x x 1 x 1 4 00100 010 x x x x x x 5 00101 011 x x x x x x 6 00110 100 x x x x x x 7 00111 101 x x x x x x 8 01000 110 x x x x x x 9 01001 111 x x x x x x 10 01010 000 1 1 1 x x 0 11 01011 000 1 1 1 x x 1 12 01100 000 0 0 1 0 x 0 13 01101...

Page 772: ...hich need more states and or faster state decoding without needing many HSRs 15 01111 000 0 0 1 1 x 1 16 10000 000 0 1 0 0 x 0 17 10001 000 0 1 0 0 x 1 18 10010 000 0 1 0 1 x 0 19 10011 000 0 1 0 1 x 1 20 10100 000 0 1 1 0 x 0 21 10101 000 0 1 1 0 x 1 22 10110 000 0 1 1 1 x 0 23 10111 000 0 1 1 1 x 1 24 11000 000 1 0 0 0 x 0 25 11001 000 1 0 0 0 x 1 26 11010 000 1 0 0 1 x 0 27 11011 000 1 0 0 1 x ...

Page 773: ... 1 Trans 2 Match 2 Trans 1 In Output Pin State1 Channel Flag1 Channel Flag0 0 00000 01x x x x 0 x 0 1 00001 01x x x x 0 x 1 2 00010 01x x x x 1 x 0 3 00011 01x x x x 1 x 1 4 00100 10x 001 x x x x x x 5 00101 11x x x x x x x 6 00110 000 1 0 0 0 x x 7 00111 000 1 0 0 1 x x 8 01000 000 x 1 0 0 0 0 9 01001 000 x 1 0 0 0 1 10 01010 000 x 1 0 0 1 0 11 01011 000 x 1 0 0 1 1 12 01100 000 x 1 0 1 0 0 13 01...

Page 774: ... 0 1 0 1 1 20 10100 000 x 0 1 1 0 0 21 10101 000 x 0 1 1 0 1 22 10110 000 x 0 1 1 1 0 23 10111 000 x 0 1 1 1 1 24 11000 000 x 1 1 0 0 0 25 11001 000 x 1 1 0 0 1 26 11010 000 x 1 1 0 1 0 27 11011 000 x 1 1 0 1 1 28 11100 000 x 1 1 1 0 0 29 11101 000 x 1 1 1 0 1 30 11110 000 x 1 1 1 1 0 31 11111 000 x 1 1 1 1 1 Host Service Request 1 The ETPUCxCR bit ETPD selects between input and output pin state T...

Page 775: ...h1 2 is disabled for one microcycle during TST see Section 23 4 1 2 Time Slot Transition and is re enabled when Entry Point is loaded if ME 1 Note that if the comparator is in equal only mode and the time base reaches the value of the Match register during the time that recognition is disabled beginning of TST plus whole thread if ME 0 the match recognition is lost If the comparator is in greater ...

Page 776: ...respect to Host and CDC accesses and so are coherent with their dual parameter coherent transfers For more details see Section 23 4 4 Parameter Sharing and Coherency No instructions are executed at the Engine where the time slot transition period occurs but the other Engine can execute normally Match1 2 is unconditionally disabled on the second TST microcycle if IPAC1 2 0xx respectively During the...

Page 777: ...AM Wait T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 DIOB END Y Entry Addr Y1st Inst Addr Entry Point Y 1st Inst CHANNEL X CHANNEL Y X END TST1 TST2 TST3 Y 3rd Inst Preload P DIOBPP 1 Pentry point PP TIME SLOT TRANSITION DIOBPP 0 DIOBentry point PP Y2nd Inst Addr MEF Y 1st Inst Y 2nd Inst Y 2nd Inst Y 3rd Inst Y 3rd Inst Addr Y4th Inst Addr HSR sampled for Flags for Entry Point Entry Point and Branch...

Page 778: ... ERT1 ERT2 Preload HSR sampled for Flags for Entry Point μPC μINST SPRAM Wait T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 DIOB Entry Point and Branch Condition END Y Entry Addr Y1st Inst Addr Entry Point Y 1st Inst CHANNEL X CHANNEL Y X END TST1 wait TST1 TST2 TST3 Preload P TIME SLOT TRANSITION Y2nd Inst Addr MEF DIOBPP 1 DIOBPP 0 Y 1st Inst Pentry point PP DIOBentry point PP X Y ...

Page 779: ...END field active see Section 23 4 9 4 1 Ending Current Thread END a forced END by host writing to the ETPUECR bit FEND see Section 23 3 2 5 ETPUECR eTPU Engine Configuration Register System Clock CHAN Register END Signal ERT1 ERT2 Preload SPRAM Wait T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 DIOB CHANNEL X CHANNEL Y X END TST1 wait TST1 wait TST1 TST2 TST3 Y 1st Inst Preload P TIME SLOT TRANSITION ...

Page 780: ...CR eTPU Module Configuration Register The watchdog can be configured in one of the following modes defining how the internal watchdog count is reset Thread Length Mode the watchdog count is reset at the end of each thread Busy Length Mode the watchdog count is reset when the microengine goes idle A sequence of threads one right after another keeps the count running The counter is also reinitialize...

Page 781: ...U integration if not used with a DMA NOTE Interrupt and Data Transfer requests can be cleared even when Engines are in Module Disable Mode through the Global Channel Registers and also DMA completion for Data Transfer requests Channel Interrupts and Data Transfer Requests can only be issued by eTPU microcode through one of the Channel Control instruction fields see Section 23 4 9 3 10 Channel Inte...

Page 782: ...annot be sensed by the Host Therefore Global Exceptions cannot be used as a normal interrupt source it should only be used for emergency procedures 23 4 2 2 2 Interrupt and Data Transfer Request Overflow If a Channel Interrupt was issued its status bit is still set and microcode issues another Channel Interrupt the Interrupt Overflow status bit is set for that channel Interrupt Overflow status can...

Page 783: ...3 1 Memory Map Accesses from the Host to the PSE area differ from accesses to the standard SPRAM address space as follows Writes the most significant byte of the parameters is not written and the SPRAM retains the old byte value regardless of the Host access size Reads the most significant bit of the 24 bit parameter that is the msbit of the second most significant 32 bit parameter byte is repeate...

Page 784: ...PUC3CR CPBA 0x172 ETPUC30CR CPBA 0x180 ETPUC31CR CPBA 0x16E ETPU2 Channel 3 Parameters ETPU2 Channel 0 Parameters ETPU1 Channel 0 Parameters ETPU1 Channel 1 Parameters ETPU2 Channel 30 Parameters ETPU2 Channel 2 Parameters ETPU1 Channel 2 Parameters ETPU1 Channel 31 Parameters ETPU1 Channel 3 Parameters ETPU1 Channel 30 Parameters ETPU2 Channel 31 Parameters 0x200 Real Parameter Number 0x014 0x020...

Page 785: ... of HSRs is completely asynchronous with Host accesses and there is no race free manner to change an HSR value before service thread execution so generally the safe way is write HSR 0 only when HSR 0 Error recovery or emergency host procedures may require one to the safely abort service and reset channel state when an HSR is already pending or executing In these cases the procedure below should be...

Page 786: ... the value read comes from the register ETPUSCMOFFDATAR The Host can program the register at initialization with an opcode value with operations that try to protect or recover the system from runaway code for instance terminate the thread clear channel flags disable match and transition service requests issue an interrupt jump to an error recovery procedure1 Table 23 18 SCM Clocks and MISC activat...

Page 787: ... it dynamically If the Host disables a channel when it is currently being serviced channel service thread will complete This means that it is possible for the output level of a channel signal to change or a Host interrupt occur even after its priority register was written to null For instance if an output transition is scheduled the transition will occur even after the channel is disabled Service ...

Page 788: ...cheduler Service Grant bit is asserted If only high level channels constantly receive service first because of their priority level middle and low level channels would only be serviced by default i e if no high level channels request service To ensure that each priority level receives an opportunity for servicing every time slot has a fixed priority level that the Scheduler honors first Divided in...

Page 789: ...uesting middle level channel If this level has no request the Scheduler continues to the low level If no requests occur the Scheduler truncates the seven state cycle and starts a new cycle at time slot one waiting for the first request Granting service to a different level channel is called priority passing The order of passing always gives the highest priority to the assigned level and the second...

Page 790: ... of cycle D 23 4 3 2 2 Priority Passing Disabling The priority passing scheme allows a case where a high priority channel looses to a lower priority one right after another lower priority has been serviced exemplified in the Cycle D on Figure 23 35 A middle priority channel wins time slot 1 due to priority passing from high to middle While it is being serviced two new service requests arrive one h...

Page 791: ...ssigned to High The second high priority channel is serviced on the next time slot jumped to 7 because there is no middle request ending cycle B Cycle C starts with time slot 2 as there are no high priority requests and two middle and two low ones After the first middle service time slot count skips 3 assigned to high no high requests and services a low priority channel on time slot 4 It follows t...

Page 792: ...t the end of the thread the service grant bit is negated no more requests of high priority level channels 2 The Scheduler proceeds to time slot two which has middle level priority however no middle level channel is requesting service Priority is passed to the high level but no high level channel is requesting service therefore priority is passed again and service is granted to the single requestin...

Page 793: ...el which requests service This channel s service grant bit is asserted The Scheduler checks again at the end of the thread All grant bits of middle level requested channels are asserted therefore all middle priority channels have been allocated execution time Under this condition all service grant bits of the middle level serviced channels are negated The Scheduler proceeds to time slot five Meanw...

Page 794: ... SPRAM to from the locations on SPRAM where parameters are accessed directly by the channels Coherency is guaranteed by SPRAM access arbitration Although limited to two parameters only it has lower latency and wastes no microengine resources1 CDC usage is described in Section 23 4 4 3 Coherent Dual parameter Controller CDC For parameters shared by both Engines eTPU provides Hardware Semaphores Coh...

Page 795: ...es only to Microengine Host coherency For Microengine Microengine coherency in a dual eTPU Engine system one must use Hardware Semaphores see Section 23 4 4 4 Hardware Semaphores Microengine dual back to back accesses are guaranteed to be atomic in relation to Host Skyblue accesses or Coherent Dual parameter Controller regardless of semaphore usage Host or CDC accesses cannot break up a back to ba...

Page 796: ...t states from SPRAM arbiter meaning 9 Skyblue wait states to Host so that it does not break atomic back to back accesses from microengine s CDC also cannot break TST preload accesses Host can initiate CDC back to back transfers there is no need of idle Skyblue cycles between two transfers 23 4 4 3 1 CDC Programming The Coherent Dual parameter Controller Register see Section 23 3 2 2 ETPUCDCR eTPU ...

Page 797: ...crocode in a way which locks semaphores for the shortest required period and frees them without waiting for the END command to improve the performance of the other microengine Semaphores are free after reset An Engine can only free a sempaphore locked by itself Semaphore lock requests are always non blocking in the sense that they do not suspend the requester in case the semaphore is already locke...

Page 798: ...e first preload are never considered a back to back access On the other hand the TST preload accesses are considered back to back and are therefore atomic with respect to Host or CDC NOTE The Zero SPRAM operation see Section 23 4 9 1 5 Zero SPRAM Operation is considered an SPRAM access for arbitration purposes both on writes and reads the fact that read SPRAM data is discarded is irrelevant for ar...

Page 799: ...istinct Transition detections can be programmed individually for each channel allowing recognition of all possible combinations of edge detection It is also possible to check the sampled state of an input signal upon the occurrence of a Match the sampling of the expected value is treated as a Transition even if the input signal did not necessarily toggled at the time of the Match or at any time at...

Page 800: ... service requests originated in the eTPU Enhanced Channels either time base match input signal transition or link service request result in a call to the corresponding channel service routine which is the sequence of microinstructions that is called a Thread For further detail refer to Section 23 4 1 Functions and Threads In addition to Event Logic each Channel has an Output Buffer Enable signal c...

Page 801: ...ic 2 Trans 2 Match2 OPAC2 IPAC2 EDF Output FF Output Logic Set Rst OBE FF ucode TBS1 2 0 PDCM SRI SRI ucode MTD Rst Set ucode PDCM ucode IPAC1 ucode IPAC2 ucode OPAC1 ucode OPAC2 Output Signal Output Buffer Enable ETPUTBCR CDCF to branch PSTI to branch PSTO PSC PSCS ucode Channel Flags Flag0 Flag1 ucode FLC Comparator Comparator ODIS OPOL Microengine Microengine MEF Filter ucode TDL ucode TDL to s...

Page 802: ... copy of them for each channel Microcode can access registers from only one channel at a time The Channel Selection CHAN register see Section Channel Selection Register CHAN accessible only by microcode defines the channel whose registers are being accessed with exception of link register and function mode CHAN register assumes the value of the channel to be serviced at the beginning of TST The Se...

Page 803: ...values of the new selected channel are sampled into Microengine registers ERT1 and ERT2 therefore becoming visible to the microcode At the same time updated values of MRL1 MRL2 TDL1 and TDL2 are sampled into the branch logic making the register values and the flags coherent with respect to each other and with the thread selected by the Scheduler1 NOTE The Function Mode bits are also sampled from t...

Page 804: ...pture1 2 registers are copied into ERT1 2 microengine registers For more information see Section 23 4 5 3 Transition Detection and Time Base Capture TBS1 and TBS2 Time Base Selection Registers TBS1 2 are 3 bit registers which have the following effect on channel configuration Selection of the timebase TCR1 or TCR2 to be compared against the match values in Match1 and or Match2 registers Table 23 2...

Page 805: ...le See Section 23 4 5 2 3 MRLE1 2 Match Recognition Latch Enable TDL1 2 Transition Detection Latch See Section 23 4 5 3 1 TDL1 2 Transition Detect Latches TCCE1 Transition Continuous Capture Enable See Section 23 4 5 3 2 TCCE1 Transition Continous Capture Enable 23 4 5 1 2 Pin Control Registers Pin Control Registers are replicated one per channel accessed only by microcode and qualified by the CHA...

Page 806: ...d the User Defined Channel Mode UDCM and the microcode Pin State Control PSC and PSCS fields It is responsible for setting the Pin State Output PSTO register to the specified logic value required by microcode by input events or by Match1 and or Match2 events The PSTO register stores the driven pin state determined by the Pin Control logic The Output Buffer Enable signal if used at MCU integration ...

Page 807: ...er to Section Match Transition Pin Action Conflict Resolution PSTI and PSS Pin State Input and Pin Sampled State Registers During the time slot transition period or whenever the CHAN register is written by microcode the filtered1 input signal PSTI or output signal PSTO selected by the ETPUCxCR bit ETPD is sampled into the branch logic as the PSS flag see Figure 23 40 and Table 23 94 The microcode ...

Page 808: ...the Output Buffer Enable signal which can be used depending on MCU integration to control the output signal pad driver Channel output comes disabled from reset If ipp_obe_ 1 2 0 31 1 from eTPU is used on MCU integration and a signal is desired to be output in a channel OBE signal must be set by microcode Microcode field TBS1 is used to set reset the Output Buffer Enable control when microcode fiel...

Page 809: ...e unique per channel Table 23 27 summarizes the registers and access options DIGITAL FILTER Q D CHAN Transition Q S R from output logic to branch logic PSTO PSS to branch logic PSTI Input Pad PSTI Q S R from TBS1 eTPU MCU Integration Output Pad and ETPUCxCSR OBE to ETPUCxCSR ODIS OPOL fromETPUCxCR 0 0 1 1 Set Reset 0 1 fromETPUCxCR ETPD SYNCH 1 0 CDFC 01 OBE channel input channel output ODIS Q D C...

Page 810: ...is written accesses are qualified by the new CHAN register value from the instruction following CHAN assignment on except Capture 1 2 sampling into ERT1 2 and Match register writing from ERT1 2 see Section 23 4 9 6 5 CHAN assignment Read Match and ERW1 2 Writing CHAN including with the same value CHAN CHAN updates ERT1 and ERT2 with the new captured values the branch logic with updated MRL1 2 and ...

Page 811: ...0 on reset PDCM is also used to select the User Programmable Channel Mode If this selection is made the channel behavior is defined by the settings of the UDCM register see Section UDCM User Defined Channel Mode Branch using PSS PRSS PSTI and PSTO channel flags YES Branch using MRL1 2 TDL1 2 Flag0 11 YES Branch on all other conditions2 no ERT1 2 Value YES configure selected channel YES channel com...

Page 812: ...e 23 41 UDCM Register SRI Match Transition Service Request Inhibit Latch SRI blocks channel service requests due to the assertion of MRL1 2 and or TDL1 2 SRI does not affect recognition of Link Service Requests or Host Service Requests neither MRL1 2 or TDL1 2 microcode branch tests nor Entry Table selection1 SRI is asserted during reset and is controlled by microcode field MTD Table 23 29 PDCM en...

Page 813: ...ons to the Match Recognition Registers MRL1 2 To recognize the match and assert these registers the following match enabling conditions are required For IPAC1 2 0xx Match Enable Flag MEF qualified by the channel currently being serviced must be asserted For IPAC1 2 1xx match1 2 is always enabled even during Time Slot Transition TST regardless the state of the Match Enable Flag MEF See Section 23 4...

Page 814: ...rence of Match2 1 in a first win scheme It is the transition from 0 to 1 in MRL that causes the Match actions apart from MRLE1 2 negation s no action due to a Match occurs if MRL was already set to 1 even if the other MRL assert conditions are satisfied However if a Match and a microoperation negating its corresponding MRL occur at the same time MRL negation by microcode overrides its assertion bu...

Page 815: ...ditions continue after writing Match1 2 registers the respective MRLE does not keep asserted For instance if MRL 1 and a match is programmed for a time value in the past during a thread with MEF 1 then MRLE will be cleared soon after Match1 2 is written even though a match does not occur because MRL was already asserted neither captures nor pin toggles occur When the match register is updated with...

Page 816: ...d captures due to Transition Events also occur after TDL1 is asserted Those captures happen on transition events specified by IPAC1 and the TCR value is saved into Capture1 register only The capturing scheme is defined by the Channel Mode programmed at register PDCM or at register UDCM when User Defined Channel Mode is selected For more information on mode dependent capture schemes refer to Sectio...

Page 817: ...ng TDLs occur at the same time and TDL was already negated TDL negation by microcode overrides its assertion but any dependable captures and pin action occurs anyway 23 4 5 3 2 TCCE1 Transition Continous Capture Enable TCCE1 enables capture from transitions after the TDL1 flag is set TCCE1 is negated on reset so that a capture occurs only when TDL1 asserts TCCE1 can be set and reset by microcode o...

Page 818: ... M1BM2 M2BM1 M2BT T1BM1 T2BM1 TBM2 and T1ET2 are decoded from programmed channel mode PDCM in predefined modes and come directly from the UDCM register when user defined mode is selected TSR 1 bit defines Service Requests issued by Transitions as shown in Table 23 31 MSR 2 bits defines Service Requests issued by Matches as shown in Table 23 30 TCAP 1 bit defines time base captures caused by Transi...

Page 819: ...equest on the 2nd3 Transition 3 2nd Transition means the Transition that happens second in time either Transition 1 or Transition 2 Table 23 32 MCAP signal Match Capture value MCAP 0 Match 1 captures Time Base 1 Match 2 captures Time Base 2 1 either Match captures both1 Time Bases 1 Match capture s never overrides a Transition capture Transition captures can always override a Match capture Table 2...

Page 820: ...T T1BM1 T2BM1 TBM21 T1ET2 TSR1 1 signals TSR TCAP and TBM2 replace the signal DTM used in previous eTPU versions TCAP1 em_nb_st 11 0 off off off off off On off 0 On 0 0 em_nb_dt 11 0 off off off off off On off 1 On 1 1 em_b_st 11 1 off off On On off On off 0 On 0 0 em_b_dt 11 1 off off On On off On off 1 On 1 1 bm_st 10 0 off off off off off On off 0 On 0 0 bm_dt2 2 bm_dt and sm_dt are exceptions ...

Page 821: ...1EM2 Match1 SR Match2 SR Trans1 SR Trans2 SR MSR 1 MSR 0 MSR 0 MSR 1 TCAP Capture2 MCAP NOTE all flip flops but MRLE reset dominant load enable Capture1 MCAP load enable sm_st_e MEF Channel Service Non filtered Trans Detection 2 1 0 TBM2 T1BM1 all control signals active high IPAC1 2 MEF Channel Service IPAC2 2 ucode MRLE MRLE sm_st_e TSE1 1 0 TSR TSE1 TSE2 Angle Tooth Detection Window channel 0 on...

Page 822: ... override a Match capture either in predefined or user defined modes The following general rules apply to both predefined and user defined modes Blocking of one Match by the other when it occurs is done through MRLEs Matches always block themselves by resetting their own MRLEs Match 1 always blocks Match 1 Match 2 always blocks Match2 Predefined modes differ mostly by the way matches affects and a...

Page 823: ...d time base and does not block the other S R Q TDL1 T2 S R Q MRL1 T2 T4S R Q MRLE1 sysclk Comparator 1 ucode ERW1 SRI Trans Event 1 S R Q TDL2 T2 S R Q MRL2 T2 T4S R Q MRLE2 sysclk Comparator 2 ucode ERW2 ucode TDL Trans Event 2 ucode MRL1 ucode MRL2 Match1 SR Match2 SR Trans1 SR Trans2 SR Capture2 load enable Capture1 load enable MEF Channel Service Double Trans 1 0 Double Trans Double Trans NOTE...

Page 824: ...ultaneous match recognition both MRL1 and MRL2 are set and OPAC2 register has priority over OPAC1 for selecting the pin action S R Q TDL1 T2 S R Q MRL1 T2 T4S R Q MRLE1 sysclk Comparator 1 ucode ERW1 SRI Trans Event 1 S R Q TDL2 T2 S R Q MRL2 T2 T4S R Q MRLE2 sysclk Comparator 2 ucode ERW2 ucode TDL Trans Event 2 ucode MRL1 ucode MRL2 Match1 SR Match2 SR Trans1 SR Trans2 SR Capture2 load enable Ca...

Page 825: ...transition modes bm_dt blocks Match1 with Transition 2 not with Transition 1 so that the second transition blocks both matches S R Q TDL1 T2 S R Q MRL1 T2 T4S R Q MRLE1 sysclk Comparator 1 ucode ERW1 SRI Trans Event 1 S R Q TDL2 T2 S R Q MRL2 T2 T4S R Q MRLE2 sysclk Comparator 2 ucode ERW2 ucode TDL Trans Event 2 ucode MRL1 ucode MRL2 Match2 SR Trans1 SR Trans2 SR Double Trans Capture2 load enable...

Page 826: ...rates a match service request and blocks both transitions S R Q TDL1 T2 S R Q MRL1 T2 T4S R Q MRLE1 sysclk Comparator 1 ucode ERW1 SRI Trans Event 1 S R Q TDL2 T2 S R Q MRL2 T2 T4S R Q MRLE2 sysclk Comparator 2 ucode ERW2 ucode TDL Trans Event 2 ucode MRL1 ucode MRL2 Match1 SR Match2 SR Trans1 SR Trans2 SR Capture2 load enable Capture1 load enable Double Trans 1 0 Double Trans Double Trans 1 0 Dou...

Page 827: ...as no effect 1 0 Double Trans S R Q TDL1 T2 S R Q MRL1 T2 T4S R Q MRLE1 sysclk Comparator 1 ucode ERW1 SRI Trans Event 1 S R Q TDL2 T2 S R Q MRL2 T2 T4S R Q MRLE2 sysclk Comparator 2 ucode ERW2 ucode TDL Trans Event 2 ucode MRL1 ucode MRL2 Match2 SR Trans1 SR Trans2 SR Double Trans Capture2 load enable Capture1 load enable Double Trans NOTE all flip flops but MRLE reset dominant all control signal...

Page 828: ...output channel it has the same functionality of sm_st captures both time bases at once due to a match recognition S R Q TDL1 T2 S R Q MRL1 T2 T4S R Q MRLE1 sysclk Comparator 1 ucode ERW1 SRI Trans Event 1 S R Q TDL2 T2 T4S R Q MRLE2 sysclk ucode ERW2 ucode TDL Trans Event 2 ucode MRL1 Match1 SR Match2 SR Trans1 SR Trans2 SR Capture2 load enable Capture1 load enable Double Trans Double Trans S R Q ...

Page 829: ...ngle Transition Double Match em_nb_st bm_st m2_st m2_o_st Double Transition Single Match em_b_dt sm_dt Double Transition Double Match em_nb_dt bm_dt m2_dt m2_o_dt S R Q TDL1 T2 S R Q MRL1 T2 T4S R Q MRLE1 sysclk Comparator 1 ucode ERW1 SRI Trans Event 1 S R Q TDL2 T2 T4S R Q MRLE2 sysclk ucode ERW2 ucode TDL ucode MRL1 Match1 SR Match2 SR Trans1 SR Capture2 load enable Capture1 load enable S R Q M...

Page 830: ...imeout mechanisms with one service request Note that although TDL1 assertion does not block Match2 recognition the value captured in Capture1 by TDL1 assertion is not overwritten by this recognition The second transition blocks match2 Either match performs timebase captures which do not overwrite captures by transitions Either Match Non Blocking Single Transition em_nb_st On an input signal this i...

Page 831: ...following MRL1 assertion The transition1 detection asserts TDL1 blocks both matches captures both timebases and generates service request Using this mode the channel can replace software open window filtering of qualified transitions with the channel hardware window The window opening and timeout can be scheduled for any of the two time bases or combination of them Typically Match1 will be used to...

Page 832: ...inst two time bases to indicate if the pulse has not ended when both MRL1 and MRL2 are asserted When a transition service request is generated by TDL2 assertion the state of MRL1 and MRL2 indicates which timeout condition occurred if any Ordered Mode with Match2 Request Single Transition m2_o_st On an input channel this mode provides a closing window filter for a single signal transition Match1 as...

Page 833: ...ce Capture1 and Capture2 copied into ERT1 and ERT2 holds the time of the qualified transition detection ERT1 and the time of the last signal transition at the input of the digital filter ERT2 Subtracting the time in ERT2 from the time in ERT1 provides the delay of the digital filter In a quiet environment the two captures provide the accurate delay of the digital filter in granularity of two syste...

Page 834: ...s can be used for Scheduling a required pin action to the first match recognition of two different time bases Cancelling a programmed pin action scheduled on one time base by match on another timebase as a consequence of Table 23 36 Microcode has to set the OPAC register of the cancelling match to no action and the OPAC register of the other match to the required pin action which may be blocked If...

Page 835: ...tion can program once the same transition time to match1 and match2 with a required pin action and on the next service program double match for the new state Another usage is generating a required pin action on one programmed time and service request later on another time after the second match recognition occurs or capturing some timebase on one time and generating a required signal transition an...

Page 836: ...ng high current output devices The signal after the high current driver feeds back to the channel input The input signal is normally delayed from the output signal by the device turn on delay After the channel output turns on the channel logic must check if the driver output connected to the channel input follows the driven value after the maximum device turn on delay If it does not the driver out...

Page 837: ...w otherwise it stays high Match 2 sets output high In both cases a service request is issued microcode intervention at the beginning and at the end of the pulse Match 2 if required SRI 0 NOTE When IPAC 1xx a match event can cause simultaneously a Match recognition and a Transition detection Depending on the Channel Mode these Match and Transition may have conflicting effects on other Transition Ma...

Page 838: ...ch 1 Match 2 Input signal Output signal IPAC1 100 OPAC1 100 Match1 window open time input sampling IPAC2 000 OPAC2 001 Match2 window close time Match1 pulse width PDCM em_nb_dt Example 2 Pulse generation on windowed input transition Example 3 Pulse generation on input sampling Example 1 Short circuit protection feedback IPAC1 100 OPAC1 001 Match1 output activate time IPAC2 100 OPAC2 100 Match2 Mat...

Page 839: ...y always access the serviced channel LINK and LSR regardless of the value written in CHAN If microcode executes an instruction with field LSR 0 clear Link Service Request the link branch condition is cleared However the link service request itself is cleared only if no link was received by the serviced channel during the same thread1 If microengine clears LSR of its channel and simultaneously Link...

Page 840: ...same value the input signal state is updated Note that when the FPSCK field selects the system clock divided by two the EDF works like the TPU1 four clock digital filter 23 4 5 6 2 Three Sample Mode In this mode like in the TPU2 3 mode the EDF uses the filter clock as a sampling clock The EDF compares three consecutive samples If all three samples have the same value the input signal state is upda...

Page 841: ...mple a two sample digital filter must sample two points in the pulse to detect it Table 23 38 shows the minimum guaranteed detected pulse width and the maximum filtered noise pulse width The table refers only to the digital filter operation The external un synchronized pulses must be wider by two extra system clocks to ensure detection through both the synchronizer and the digital filter Delays in...

Page 842: ... the Red Line bus and can only be read by microcode For information on Red Line bus protocol and definition of Red Line modules refer to IPI Red Line and Section 23 4 6 3 Red Line Interface The TCR2 counters between the two Engines are out of phase by 1 system clock even when Time Bases are shared between them through Red Line It also applies to TCR1 counters if ETPUTBCR TCR1CS 0 but they can be i...

Page 843: ...arts a new count and the new TCR1P becomes effective When TCR1 is written by microcode the prescaler is reloaded with TCR1P and it becomes effective if etpu_gtbe_in is asserted 23 4 6 1 4 Red Line STAC Bus Client Mode In this mode the TCR1 register is continuously updated from the Red Line STAC bus and the clock selection and prescaling logic becomes ineffective It is not writable by the microcode...

Page 844: ...gle clock and angle counter Figure 23 53 shows the diagram for TCR2 clock control When TCR2 is not driven by the EAC or Red Line the ETPUTBCR field TCR2CTL selects the clock source also allowing TCR2 to be frozen independently of TCR1 see Section 23 3 3 1 ETPUTBCR eTPU Time Base Configuration Register When in Angle Mode TCR2CTL selects the TCRCLK edge sensitivity Figure 23 53 TCR2 Clock Control Th...

Page 845: ...guration Register The TCR2 Prescaler resets when etpu_gtbe_in is negated After reset it starts counting up to TCR2P when etpu_gtbe_in is asserted When TCR2 increments etpu_gtbe_in 1 the prescaler starts a new count and the new TCR2P becomes effective When TCR2 is written by microcode the prescaler is reloaded with TCR2P and it becomes effective if etpu_gtbe_in is asserted The counter that divides ...

Page 846: ... by eight Therefore the Red Line update rate for the Angle Bus must not be slower than eight system clocks 23 4 6 2 6 TCR2 Bus in Angle Clock Mode In this mode the TCR2 counter operates as part of the eTPU Angle Counter EAC The TCR2 bus value reflects this angle representation in which it counts Angle Ticks Angle Mode is selected when the AM bit is set in ETPUTBCR Note that when TCR2 works in Angl...

Page 847: ...efer to Section 23 4 7 EAC eTPU Angle Counter Proper configuration of the following bits is necessary to determine what can drive the Red Line bus ETPUTBCR AM and ETPUREDCR REN2 RSC2 according to Figure 23 39 Note that Angle Mode is not available for Red Line bus clients configuring both at the same time brings unpredictable results When TCR2 is a stand alone counter or a Red Line Bus server the s...

Page 848: ...two block interface signals etpu_gtbe_out and etpu_gtbe_in GTBE bit sets etpu_gtbe_out and etpu_gtbe_in enables time bases to start The etpu_gtbe_out signal can be used by MCU integration for synchronization between eTPU time bases and time bases from other modules If the GTBE bit in ETPUMCR must enable only the eTPU time bases etpu_gtbe_out is simply connected to etpu_gtbe_in These two cases are ...

Page 849: ...the channel filters see Table 23 9 The TCRCLK filter delay and prescaling determines the minimum detectable TCRCLK pulse widths and therefore its maximum frequency as shown in Section 23 4 5 6 4 Filter Clock Prescaler and Table 23 38 The TCRCLK signal delay from the module input to TCR1 TCR2 incrementing or detection in the EAC logic is explained in Section 23 6 1 2 Input Output Signal Delays 23 4...

Page 850: ... channel Channel 0 1 or 2 generates the signal transition service request and can also be used for generation of a window filter on this transition to qualify TCR2 clocks For this purpose the selected channel should be configured with double match window filtering mode refer to Section 23 4 5 4 Channel Modes Depending on the channel mode set for the channel Match1 recognition opens the window and ...

Page 851: ...n about the use of this register Figure 23 55 provides a detailed description of TPR register Several conflict issues on TPR writes are explained in Section 23 4 7 12 Special TPR Write Cases Figure 23 55 TPR Register LAST Last Tooth Indication Asserted by microcode and negated when a tooth is detected or inserted via IPH 1 Last Tooth reset TCR2 Counter at the end of the tooth tick count after phys...

Page 852: ...eeze mode until a new physical tooth a real one or emulated with IPH 1 is detected Assertion of this bit immediately freezes the EAC in the middle of the tooth period When a new physical tooth is detected the bit is automatically negated by the EAC The HOLD bit can be used for synchronizing the EAC tooth count in case that a false physical tooth is detected due to noise 1 Force EAC to halt until d...

Page 853: ...Mode physical tooth detection is done by EAC regardless of the value set in TCR2P 23 4 7 2 3 TRR Tick Rate Register The exact period of the Angle Tick is programmed in the Tick Rate Register by microcode The period of the Angle Tick is given in units of TCR1 clocks as system clocks divided by 2 TCR1P 1 even if TCR1CS 1 see Section 23 3 3 1 ETPUTBCR eTPU Time Base Configuration Register Refer to Se...

Page 854: ...raction Accumulator and whenever the result overflows i e the accumulated fraction added up to an integer the Tick Prescaler is halted for one TCR1 clock Figure 23 58 EAC PLL FILTER TCR1 clock divided by TRR TICK COUNTER MICROCODE Estimated Tooth Time New TRR Tick clock TCR1 clock PHYSICAL TOOTH CAPTURED TCR1 TICKS TOOTH TICKS TCR2 TIME EAC CHANNEL CAPTURE1 TCR1 EAC CHANNEL CAPTURE1 TCR1 EAC CHANN...

Page 855: ... Channel 0 in Angle Mode Angle Mode Tooth Program Register 24 Integer Fraction Fraction Accumulator 9 9 Carry 9 Tick Prescaler 15 Angle Tick TCR1 Clock Hold Din 24 10 24 Angle Tick Generator Angle Counter Logic H Rate Load Angle Tick Inc Hold Angle Mode Ticks Angle Tick Reset 2 Last Tooth AM ETPUTBCR AM ETPUTBCR To Channel 0 Edge Detection override its digital filter Edge Detect Count Filtered Pin...

Page 856: ...r external Red Line clients if TCR2 is a Red Line server which compare angle in equal mode These peripherals must get all the valid angle values in a sequential manner to avoid missing angle matches TCR2 advancing from one tooth to another is a continuous count and can be optionally reset at the end of the tooth An estimated tooth is generated after the Tooth Tick Counter reaches the TICKS program...

Page 857: ...e represented with 24 bits Using shift left nine positions and one divide operation would get the result in MACL register in MDU which holds the integer and nine bits of the fraction Angle_Tick_Rate Integer 14 0 Fraction 8 0 TCR1ToothPeriod2 9 Ticks TRR Angle_Tick_Rate Integer 14 0 Fraction 8 0 On low RPM the initial tooth period measured in TCR1 counts may be too big to be shifted nine positions ...

Page 858: ...nteger and the fraction parts The accuracy depends on the bit count of the fraction Using 9 bit fraction part while the width of the field TICKS in register TPR is 10 bits provides accuracy of two LSB on a full scale TICKS 1023 or one LSB on lower scale TICKS 511 When the Tick Prescaler gets High Rate mode indication from the Angle Counter Logic it generates angle ticks at a rate of system clock d...

Page 859: ...Enhanced Mode refer to Section Single Match Enhanced Mode sm_st_e is capturing a single time base due to signal transition before and after the digital filter This option allows subtracting the digital filter delay to get accurate signal transition timing on the channel This way the TCRCLK signal may be programmed with a slow and reliable digital filter and get accurate time measurement of the dig...

Page 860: ...0 if TPR bit LAST is asserted See Figure 23 62 for a detailed diagram of Halt Mode behavior The microcode service caused by the physical tooth determines the deceleration calculates the new tooth period and Angle Tick period and updates TRR This operation slows the angle tick rate generated by the Angle Tick Generator on the fly to the rate required for the new tooth period Since the microcode ser...

Page 861: ... TCR2 or resets it if LAST is asserted and MISSCNT 0 The control logic switches back to Normal Mode using the most updated TRR value as input to the Angle Tick Generator The logic samples the updated TICKS value for the tooth estimation last tooth indication and number of missing teeth from TPR In High Rate mode the angle ticks are provided at high speed until the end of the current tooth This ope...

Page 862: ...that the microcode updates of the TICKS field in TPR affect the end time of the current physical tooth For correct operation this field should be updated before the Tooth Tick Counter has reached either the old or the new TICKS value During High Rate mode operation TRR is ignored and the Angle Tick Generator uses system clock divided by eight Therefore the TRR update by microcode will take effect ...

Page 863: ...and The operation resets the TCR2 based angle count indicating a new period of the engine cycle This implementation provides an engine cycle based periodic angle measurement 23 4 7 6 2 Handling Missing Teeth The EAC can handle up to three missing teeth in two ways Count the angle ticks relative to the last physical tooth The microcode should update the TPR TICKS field to the number of angle ticks ...

Page 864: ... EAC switches to High Rate mode in order to run through all the valid angle values including the dummy teeth When the Tooth Tick Counter reaches the TICKS value on High Rate mode and the dummy tooth down counter is not zero the generated dummy tooth advances to the next tooth and decrements the dummy tooth counter but does not switch the EAC back to Normal mode The last dummy tooth decrements the ...

Page 865: ...a Match timeout event of EAC channel will call service which detects extreme deceleration The microcode can assert the IPH bit in TPR to force the detection of the missed physical tooth It can also calculate the accumulated angle bus error and fix the next estimated tooth period to close the gap 23 4 7 9 Handling False Tooth Detection Most of the false tooth detection caused by noises on the engin...

Page 866: ...oth edge detection TDL1 asserted on single transition modes TDL2 asserted on double transition modes on mode m2_st the window opens on Match1 which enables Transition1 and does not close with Match2 If Match2 comes before Match1 it blocks Match1 and hence Transition1 on mode m2_o_st the window opens on Match 1 which enables Transition1 and closes on Match2 Match2 is enabled by Match1 so it cannot ...

Page 867: ...write behaves as if EAC is still in Normal mode Only in the next microcycle after execution of a nop for instance the TPR writes are buffered acknowledging High Rate mode MISSCNT and LAST can be written any value during High Rate mode and the value that prevails for the next tooth is the one sampled when EAC goes back to Normal mode or the value written in Normal or Halt mode thereafter If MISSCNT...

Page 868: ...23 4 7 12 5 IPH and HOLD If IPH and HOLD are asserted at once IPH cancels the HOLD and both reset The EAC is not frozen regardless of the mode 23 4 7 12 6 LAST and HOLD If LAST and HOLD are written 1 at once LAST asserts and EAC is frozen When a physical tooth is detected or IPH is asserted the EAC is unfrozen in the same state it was before and LAST is kept asserted 23 4 8 Microengine Each eTPU e...

Page 869: ...PR TRR registers are accessible by microcode 24 bit ALU and Post ALU shifter performs basic arithmetic and logical operations described in Section 23 4 8 2 ALU and Post ALU Shifter MDU MAC Divide Unit performs integer MAC multiply and divide operations Fixed Microinstruction Size of 32bits Fixed length instruction execution 2 system clocks Static superscalar operation ...

Page 870: ... 4 24 24 24 24 24 24 eTPU CHANNELS ER1 Bus ER2 Bus 24 SPRAM A Bus 24 24 24 32 24 1 MACH MACL MAC 24 24 24 DIVIDE UNIT 24 AIN N V Z C MB Flags to to Branch Logic MN MV MZ MC 5 RAR Channels TCRs Microengine s DataPath Shifter EAU Shifter Result Result Address Size Calc CHAN 8 16 or 24 24 AS source 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 LINK TCR1 TCR2 6 TDL2 PSTI PSTO to Branch Logic MRL1 MR...

Page 871: ...in detail in Section 23 4 9 1 SPRAM Microoperations P is automatically loaded with one parameter before the thread starts parameter preload For more information see Section 23 4 1 1 5 Entry Point Format and Section 23 4 1 2 Time Slot Transition Upper 8 bits of P register can be used as application state since these bits can be tested as branch conditions P 31 24 is also used in dispatch microopera...

Page 872: ...2 6 Shift Operations 23 4 8 1 5 MACH and MACL Registers Both MACH and MACL are 24 bit registers part of MAC Divide unit see Figure 23 4 8 3 They can be used as source and destination in most arithmetic logic operations When multiply or divide operations are used multiply accumulate included MACH and MACL have special purpose and some restrictions apply see Section 23 4 8 3 MAC and Divide Unit MDU ...

Page 873: ...tion selection all of them can be performed including add subtract using C carry flag as ALU s carry in bitwise AND OR NOT XOR and shift rotate of 2 4 8 and 16 bits See Section 23 4 9 2 10 ALU MDU Operation Selection Subtraction inversion increment and decrement can be performed by combinations of source inversion and setting ALU s carry in to 1 ALU always performs 24 bit operations on its inputs ...

Page 874: ...tion dependent The Carry flag in add subtraction with Post ALU shift is defined in Table 23 45 Find the definitions for other operations in the following sections Negative flag N Negative flag indicates the sign of result based on the operation size regardless of the operation performed as shown in Table 23 41 NOTE The N flag may not reflect the sign of the value actually written into the destinat...

Page 875: ...OP or ALUOPI fields See Section 23 4 9 Microinstruction Set for more details Table 23 44 describes how CIN and BINV fields change ADD operation behavior Table 23 42 Overflow Flag on Addition1 V 1 for V flag definition on the absolute operation see Section 23 4 8 2 8 Absolute Value Operation Op Size Value2 2 BS is taken after any inversion by the BINV field but not added to the carry bit CIN field ...

Page 876: ...23 4 9 2 3 Flags Sampling Control For example if CCSV 00 T4ABS P 24 bits T4BBS A 24 bits T2ABD B 24 bits and ALUOP Add ROR then B gets A P with bits 7 0 rotated even though the operation size is 24 bits Table 23 45 describes Carry flag behavior Table 23 45 Carry flag update on ADD operation BINV1 Op Size shift rotate Value 1 8 bits none adder carry from bit 7 to bit 8 1 16 bits none adder carry fr...

Page 877: ...s CIN field is ignored and BINV field inverts bitwise NOT BS C and V Flags are never updated on these operations Table 23 47 Describes AND OR and XOR bitwise operations 0 8 bits rotate right adder carry from bit 7 to bit 8 0 16 bits rotate right adder carry from bit 15 to bit 16 0 24 bits rotate right alu_adder_output 24 except on max constant generation see Section Max Const Generation With T4BBS...

Page 878: ...bit BINV 0 result AS 1 31 BS 4 0 clear bit BINV 0 result AS 1 31 BS 4 0 23 4 8 2 6 Exchange Bit Exchange the AS bit determined by BS 4 0 with C flag If the bit number resolves to a value greater than 23 no exchange is performed i e result is equal to AS and C flag is not updated This operation overrides BS size to 8 bits On this operation CIN field is ignored and BINV field inverts bitwise NOT BS ...

Page 879: ...the result V and N flags are updated with the result signal determined by the operation size AS bit 23 after size override and sign extension if any see Section 23 4 9 2 8 A Source Size Override regardless of A source register size is used to check the operand signal and is copied to C flag Note that if AS is 8 bit or 16 bit its sign is taken into account and copied to C only if sign extension is ...

Page 880: ...es MDU the result is always placed in MACH and MACL registers and the register selected as destination does not have its value changed Section 23 4 9 2 2 Selecting Sources and Destination During calculations MACH and MACL holds temporary values and should not be written otherwise the result is unpredictable One must not start an MDU operation while MDU is already busy the result is unpredictable f...

Page 881: ...to be used in a multiply accumulate sequence It is also allowed to mix different sizes in multiply mac sequences Multiply accumulate operations are similar to multiply operations except that the contents of MACH and MACL registers are added to the multiplication result When multiply or multiply accumulate operations finish MACL and MACH hold the least and the most significant 24 bit words respecti...

Page 882: ...at only 24 bit multiply accumulate is available 23 4 8 3 6 Unsigned Multiply Accumulate macu MDU Unsigned Multiply Accumulate is defined as follows signed unsigned MACH MACL unsigned AS unsigned BS MC is set if result can not be represented by a 48 bit unsigned non negative number MACU never resets MC flag MC flag is left as is if no carry occurs or set otherwise This allows checking the carry fla...

Page 883: ...f a fraction with denominator 224 The concatenation of MACH and MACL form a 48 bit fixed point number with a 24 bit mantissa both for 8 and 16 bit operations MDU flags are updated in the same way as in the Unsigned Multiplication 23 4 8 3 9 Unsigned Divide div At the end of a divide operation MACL holds the result of the division taking A source as numerator and B source as denominator while MACH ...

Page 884: ... 8 4 Branch Conditions Microengine allows conditional branch There are five sets of flags that can be tested in a conditional branch ALU flags MDU flags P flags Channel flags and Semaphore flag flag SMLCK When a thread starts to be executed the values in MDU and ALU flags are not initialized ALU flags are described in Section 23 4 8 2 1 ALU Flags MDU flags are described in Section 23 4 8 3 10 MDU ...

Page 885: ...n one group Complete microinstruction formats are shown in Section 23 4 9 7 Microinstruction Formats Parallelism conflicts may arise when two operations are executed in the same microinstruction These situations are explained in Section 23 4 9 6 Microinstruction Parallelism Issues Table 23 52 Channel Flags as Branch Condition Flag Description Service or Selected Channel Flag0 State Resolution flag...

Page 886: ...Absolute addressing mode the address range is 256 parameters addressed by field AID which in this mode is 8 bit wide These parameters are located in SPRAM addresses from 0 to 255 physical_address AID 7 0 Selected Channel Relative Addressing Mode In Selected Channel Relative addressing mode only the first 8 with 3 bit AID or 128 with 7 bit AID parameters of the selected channel are accessible depen...

Page 887: ...lable in microinstructions that support SPRAM access the source destination is P 23 4 9 1 3 SPRAM Operation Size When using DIOB register to perform SPRAM data transfers the operation size is always 24 bit wide lower 24 bits of SPRAM When using P register the operation size can be 8 24 or 32 bit wide which is controlled by microcode RSIZ field 2 bits RSIZ meaning is shown in Table 23 54 RSIZ is no...

Page 888: ... 23 4 9 1 6 DIOB Stack Operation and ALU operations are resolved like a normal SPRAM operation see Table 23 98 23 4 9 1 6 DIOB Stack Operation SPRAM Indirect Addressing Mode see Section Indirect Addressing Mode is used if STC field 2 bits exists in the microinstruction controlling automatic increment decrement of DIOB register as shown in Table 23 57 thus allowing stack operations DIOB is incremen...

Page 889: ...or SHF In formats where there is no operation selection field ALUOP ALUOPI or SHF the operation performed is always addition however it is possible to perform subtraction increment or decrement using fields BINV see Section 23 4 9 2 4 B Source Inversion and CIN see Section 23 4 9 2 5 Carry in Control 23 4 9 2 1 Source and Destination Register Set Selection Microcode field T4ABS allows selection of...

Page 890: ...results are stored in MACH and MACL see Section 23 4 8 3 MAC and Divide Unit MDU ABSE and ABDE are not available in some microinstruction formats that support ALU MDU operations However in all formats where ABSE is available ABDE is also available and vice versa The existence of ABSE ABDE fields changes the meaning of T4BBS field as shown in Table 23 61 On instructions with immediate data it is us...

Page 891: ...oinstruction formats without ABSE ABDE1 1 T4BBS also selects A source and destination register set in this case according to Table 23 60 000 BS 23 0 P 23 0 001 BS 23 0 A 23 0 010 BS 23 0 SR 23 0 011 BS 23 0 DIOB 23 0 100 reserved BS 0 101 reserved BS 0 110 reserved BS 0 111 BS 0 or Max const if CIN 0 and BINV 0 see Section Generating max constant Table 23 62 A Source Selection T4ABS T4ABS First Re...

Page 892: ... 7 0 AD 7 0 8 0010 ERT1 23 0 AD 23 0 1 1 T2ABD 0010 with first register set also writes to Match1 or UDCM registers of the selected channel if field ERW1 0 see Section 23 4 9 3 5 Write Channel Match and UDCM Registers 24 TPR 15 0 AD 15 0 16 0011 ERT2 23 0 AD 23 0 2 2 T2ABD 0011 with first register set also writes to Match2 register of the selected channel if field ERW2 0 24 B 23 0 AD 23 0 24 0100 ...

Page 893: ...r address CPBA 2 can be used as A source using T4ABS 1010 when T4ABS selects a source from the second register set In this case CHAN_BASE is loaded into AS 13 2 to form the byte address AS 23 14 0 AS 1 0 0 For example in Indirect addressing mode where the destination register is DIOB CHAN_BASE is loaded into DIOB 13 2 which is the parameter address and DIOB 13 0 represents the byte address CHAN_BA...

Page 894: ...ation size When neither CCS nor CCSV are present in the microinstruction flags are not sampled CCS and CCSV do not affect the Carry update on Exchange Bit operation see Section 23 4 8 2 6 Exchange Bit but does control the N and Z flags 23 4 9 2 4 B Source Inversion The data selected as second source T4BBS can be inverted bitwise boolean NOT before operation This is controlled by microinstruction f...

Page 895: ...not inverted neither the carry out Max constant is the value which added to a time base value minus 1 gives the farthest wrapped time base value that satisfies a channel greater equal comparison See Section 23 4 5 Enhanced Channels for more info 23 4 9 2 6 Shift Operations There are three types of shift operations ALU post ALU and Shift Register ALU shift operations are covered in Section 23 4 9 2...

Page 896: ...selecting post ALU shift operation using ALUOP field ALU will always add the sources before shifting the result Carry flag is only updated when CCS or CCSV 1 0 fields allow it see Section 23 4 9 2 3 Flags Sampling Control Algorithmic descriptions of post ALU shift operations are presented in Section 23 4 8 2 2 ALU ADD Operation with and without shifting Table 23 69 Shift Register Control SRC SRC M...

Page 897: ...ion is CHAN no actions associated with CHAN assignment occur see Section Channel Selection Register CHAN the ALU and MDU flags are not updated MDU does not start any operation i e MACH and MACL are not updated SR does not shift T4ABS selected read match does not occur 23 4 9 2 8 A Source Size Override Some values if the AS CE field are used for A Source Size Override as shown in Table 23 72 Table ...

Page 898: ... to the size of A operand either overridden or not by AS CE field according to Table 23 74 The sign is taken from the size overridden value not the original one A source sign is not extended in microinstructions without SEXT field even if AS CE field is present 23 4 9 2 10 ALU MDU Operation Selection When field ALUOP is available in microinstruction enhanced ALU operations shown in Table 23 75 can...

Page 899: ...10 AS 23 0 BS 23 0 24 bit bitwise AND 10011 abs AS absolute value of AS 10100 AS BS arithmetic addition 10101 AS BS shl 1 arithmetic addition with 1 bit post ALU shift left Section Post ALU Shift Operations 10110 AS BS shr 1 arithmetic addition with 1 bit post ALU shift right Section Post ALU Shift Operations 10111 AS BS ror 1 arithmetic addition with 1 bit post ALU rotate right Section Post ALU S...

Page 900: ...h Immediate Data Enhanced operations with immediate data selected by ALUOPI 5 bits are allowed only with an 8 bit immediate operand see Table 23 77 Table 23 76 24 bit Immediate Destination T2D T2D Target Register 00 P 23 0 01 A 23 0 10 SR 23 0 11 DIOB 23 0 Table 23 77 ALU Operation Selection With Immediate Data ALUOPI ALUOPI Operation Comment 00000 AS mults imm8 signed multiplication 00001 AS mult...

Page 901: ... 15 0 AS 15 0 bitwise OR 10001 AD 23 16 AS 23 16 imm8 AD 15 0 AS 15 0 bitwise XOR 10010 AD 23 16 AS 23 16 imm8 AD 15 0 AS 15 0 bitwise AND 10011 AD 23 16 AS 23 16 imm8 AD 15 0 0x0 bitwise AND with clear 10100 AS imm8 arithmetic addition 10101 AS imm8 shl 1 arithmetic addition with 1 bit shift left 10110 AS imm8 shr 1 arithmetic addition with 1 bit shift right 10111 AS imm8 ror 1 arithmetic additio...

Page 902: ...er Enable signal See Table 23 26 Table 23 78 P Flags Operation FLC FLC Meaning 000 clear flag0 001 set flag0 010 clear flag1 011 set flag1 100 copy flag1 flag0 from P 25 24 101 copy flag1 flag0 from P 27 26 110 copy flag1 flag0 from P 29 28 111 no operation nil Table 23 79 Time Base Selection 1 TBS1 TBS1 bit 2 1 0 TBS1 3 0 bitfield Comparator selection Capture selection Match TB selection 0 greate...

Page 903: ... 4 Immediate Pin State Control It is possible to change output signal state immediately by using PSC 2 bits and PSCS 1 bit fields TBS2 3 1 action 2 1 0 do nothing 1 1 1 reserved all other values Table 23 81 Input and Output Pin Action Control IPAC1 2 and OPAC1 2 value IPAC meaning OPAC meaning 000 Do not detect transitions Do not change output signal 001 Detect rising edge only Match1 sets output ...

Page 904: ...ed channel and it is possible to clear those flags using the microcode fields MRL1 MRL2 1 bit each and TDL 1 or 2 bits depending on the format The flags cleared by these microcode fields are the actual channel flags and also the ones sampled into the branch logic TDL can be one or two bits wide depending on the microinstruction format see Section 23 4 9 7 Microinstruction Formats Two bit TDL allow...

Page 905: ...nsition service requests for the selected channel MTD does not disable Link Service Request and Host Service Request MTD sets or resets registesr SRI for more details see Section SRI Match Transition Service Request Inhibit Latch and TCCE1 see Section 23 4 5 3 2 TCCE1 Transition Continous Capture Enable MRL2 0 clear MRL2 event register 1 don t change TDL 1 bit 0 clear TDL1 and TDL2 flags 1 don t c...

Page 906: ...ation see Section 23 4 2 2 Interrupts and Data Transfer Requests Table 23 88 Disable Match and Transition Service Request MTD MTD Action on SRI Action on TCCE1 00 SRI 0 enable service requests for match and transition TCCE1 0 disable transition captures1 when TDL1 1 1 Disables only captures on transition events specified by IPAC1 01 SRI 1 disable service requests for match and transition 10 SRI 1 ...

Page 907: ...provided to repeat a given microinstruction to finish the current thread execution and to halt the microengine 23 4 9 4 1 Ending Current Thread END Microcode END field 1 bit finishes current thread and allows other channels to be serviced If END field is 0 the current instruction is completed and the thread is finished END 1 has no effect and the next microinstruction is executed Any MDU operation...

Page 908: ...Unconditional Branch Jump and call can be conditional or unconditional depending on the BCC 6 bits and BCF 1 bit fields as shown in Table 23 93 and Table 23 94 BCF determines whether branch is taken when condition specified by BCC is true or false When a branch condition uses the channel flags the channel context is related to the channel number written in CHAN register Table 23 92 Jump Call Selec...

Page 909: ...ine microoperation is affected by FLS see Section 23 4 9 4 5 Flush Pipeline when field R D is used Return execution through RTN always flushes the pipeline 100111 MZ MDU flag 110111 P 27 101000 TDL1 channel flag 111000 P 28 101001 TDL2 channel flag 111001 P 29 101010 MRL1 channel flag 111010 P 30 101011 MRL2 channel flag 111011 P 31 101100 LSR channel flag 111100 PSTO channel flag 101101 MB flag M...

Page 910: ...he branch dispatch instruction 2 even if RAR is the ALU destination of the instruction after the call in case of a flush it is the address of the instruction following branch dispatch If a branch with no flush is followed by another branch with no flush the instructions are executed in the following order 1 first branch 2 second branch 3 first branch s destination instruction 4 second branch s des...

Page 911: ...truction is achieved through any of the formats shown on Section Table 23 99 Microinstruction Formats where the user can assign to each individual field the corresponding value for No Operation However to prevent future impacts of instruction changes on object code compatibility the instruction value 0x4FFFFFFF should always be used for NOP 23 4 9 5 Illegal Instructions An instruction is considere...

Page 912: ...remains in P or DIOB after an operation when one of them is specified as destination for both ALU and SPRAM microoperations In this case the value loaded into P or DIOB is the one read from SPRAM However the ALU operation is executed and its flags are updated accordingly When P or DIOB is destination of an SPRAM read and also an ALU source at the same microinstruction the value before the read is ...

Page 913: ...d Match and ERW1 2 When CHAN is a destination of an ALU operation it causes a read of the Capture1 2 register values into ERT1 2 The Capture registers loaded into ERT1 2 are selected by the new CHAN value The value of the Capture1 2 registers overwrites any read match commanded simultaneously If CHAN assignment happens with an ERW1 2 operation in the same instruction the updated Match register s b...

Page 914: ...DIOB 15 2 DIOB write with posinc value written is before increment 23 4 9 6 8 SRC and ALU MDU operations If operation SRC is active field SRC 0 and register SR is selected as destination of an ALU operation the value of the ALU operation prevails over the shifted value The value of SR used as source in the ALU MDU operation is the one before the shift 23 4 9 6 9 Semaphore lock free and SMLCK branc...

Page 915: ...MPC563XM Reference Manual Rev 1 Freescale Semiconductor 915 Preliminary Subject to Change Without Notice 23 4 9 7 Microinstruction Formats See Table 23 99 ...

Page 916: ...6 0 channel param B3 0 0 0 STC AB SE AB DE rsv 1 1 B4 0 0 1 0 CCSV 1 AS CE ALUOP B5 FL 0 SEXT SMPR B6 1 rsv SRC AB SE AB DE B7 0 1 1 END SHF TDL PSC MRL1 ERW1 MRL2 ERW2 ABSE ABDE CCS MRLE PSCS C1 0 1 0 0 END OPAC1 OPAC2 TBS1 TBS2 LSR PDCM C2 1 IPAC1 IPAC2 D0 1 1 0 0 MRLE 0 CIRC PSC FLS RW PSCS FLC CIRC 1 0 R D 0 P D RSIZ ZRO AID 6 0 engine param D1 1 AID 7 0 global param D2 1 ZRO AID 6 0 channel p...

Page 917: ... test feature accessible through registers ETPUMCR and ETPUMISCCMPR see Section 23 3 2 System Configuration Registers MISC allows SCM test on the fly i e while eTPU is running with no impact on eTPU functionality or performance 23 4 10 2 Development Support Features 23 4 10 2 1 Internal Debug Interface and Nexus Class 3 Support eTPU provides an Internal Debug Interface that exports real time micro...

Page 918: ...DEDI register NDEDIETPUx_DC field CBI 1 If same register s field CBT 1 microengine halts at the next time slot boundary if CBT 0 it halts immediately As a particular case microengines come halted out of reset if SoC debug request is asserted since CBI reset value is 1 Microengine does not execute out of reset either in halt SoC debug request asserted or idle state SoC debug request negated but hal...

Page 919: ...uration for more details see the NDEDI Block Guide CHAN register assignment only by microcode not by time slot transition SPRAM read and or write to a given address and or write data The breakpoint is always qualified by the SPRAM address but the following variations are allowed break on write only read only or read and write break on higher byte write data value lower 24 bit write value full word...

Page 920: ...les above apply It means that if a go is issued in Halt_idle state with MDIS 1 the engine goes to Idle for one microcycle and then stops if MDIS or SoC stop request keeps asserted and there is no other breakpoint request NOTE Hardware breakpoint requests are ignored for the first microinstruction executed when microengine leaves halt 23 4 10 2 4 Hardware Watchpoints Debug Interface allows watchpoi...

Page 921: ...application standpoint after the HALT is executed the eTPU debug interface informs the address of the branch dispatch return destination and the debugger application has no direct way to identify which HALT instruction was executed if multiple HALTs lead to the same address This can be solved if the debug support block NDEDI has a register holding the address of the last instruction executed other...

Page 922: ...tion with a NOP So to clear the instruction pipeline during halt all one has to do is an unconditional branch to the desired address with flush HALT instructions must not be executed as forced Forced operations that depend on the serviced channel are unpredictable when executed in halt_idle 23 4 10 2 8 Microengine Register Access eTPU provides no direct access to microengine and channel registers ...

Page 923: ... to replace it allowing code patching and software breakpoint setting for debugging purposes SCM ROM replacement by Emulation RAM is MCU dependent The SCM may even be divided into a ROM part and a RAM part In this case both microengines can run code from both ROM and Emulation RAM It is possible to make one Engine run code from RAM and the other from ROM by using different Entry Tables The SCM vis...

Page 924: ...the last SCM address and counts down to 0 The conditions for executing a MISC operation are see also Table 23 18 Both microengines in idle state no channel is being serviced or stopped in any combination e g engine 1 idle with engine 2 stopped ETPUMCR bit VIS 0 ETPUMCR bit SCMMISEN 1 Note that MISC can run regardless of SCM implementation type RAM or ROM If SCMMISEN 0 or VIS 1 the MISC logic stays...

Page 925: ...bits Write to SPRAM for parameter initialization of each configured channel Write to channel x Host Service Request registers ETPUCxHSRR to initialize the active channels 1 Write to the channel interrupt enable register ETPUCIER if interrupts are to be enabled from the appropriate channels Likewise for Data Transfer Requests ETPUCDTRER This can be done through ETPUCxCR Write to channel x configura...

Page 926: ...s upon Host Service Request data from to a TPA to from a PPA Coherency is guaranteed by the fact that a thread is atomic with respect to other threads in the same Engine and so are its transfers If parameters in PPA are shared by both Engines hardware semaphores have to be used to access them Mailbox for Host to eTPU transfers the microcode checks a flag set by the host indicating the existence of...

Page 927: ...nd ETCS They cannot be changed when the channel is enabled If the channel is disabled first one may still have service requests from the previous function so before the channel is enabled again one must be sure that the first thread executed in the new function is the initialization one the initialization thread of the new function clears any previously pending service request Follows a safe proce...

Page 928: ...d by the first analysis the second pass WCL analysis should be applied The second pass analysis is not a generalized formula but rather uses specific system details for a realistic worst case estimation 23 5 5 1 Introduction to Worst Case Latency NOTE In this Appendix the latency calculation and examples refer to old TPU functions such as PWM DIO etc These functions use single action channels whic...

Page 929: ... to execute a thread varies with the number of microcode instructions in the thread Since there is only one eTPU Microengine in each eTPU Engine the eTPU cannot actually execute the software for multiple functions simultaneously However the hardware for each of the channels is independent This means that for example all 32 channel signals can change thread at the same moment provided that the func...

Page 930: ...hannel 5 requests service from the eTPU Microengine to execute thread 3 Thread 3 writes a time into the channel 5 match register and performs other operations that will cause the channel 5 signal to go from high to low at match time At match time the signal goes low and channel 5 requests service from the eTPU Microengine to execute thread 2 A PWM wave is kept running on the system by the eTPU exe...

Page 931: ...to channel numbers and gives each active channel a priority level of high middle or low The Scheduler uses the channel number and channel priority level to determine the order in which to grant service The scheduler allocates time slots to specific priority levels of high middle or low One function thread is executed in each time slot The length of a time slot varies according to the length of the...

Page 932: ...ee Section 23 4 1 2 Time Slot Transition Time slot transitions can take from six up to ten system clocks 23 5 5 3 3 Channel Number Priority If more than one channel of a priority level is requesting service the lowest numbered channel is granted service first For example if channels 0 5 and 9 are all high level channels requesting service during a high time slot channel 0 is granted service first ...

Page 933: ...ead write read write of one system clock each The system designer should estimate the percentage of SPRAM accesses in the system that will result in a Microengine wait due to coherent transfer and multiply it with the average number of system clocks the Microengine waits for each transfer This percentage is called Coherent Parameter Collision Rate CPCR In addition Microengine to Microengine multip...

Page 934: ...PU semaphore RAM accesses in the longest thread CCRWait Average System Clocks for Microengine Microengine communication transfer Estimated Wait Time Function eTPU maximal wait time N1 RCR RCRWait CPCR CPCRWait N2 CCR CCRWait 23 5 5 4 First Pass Worst Case Latency Analysis Following is the first pass calculation of worst case latency for a channel Remember that this analysis uses generalizations th...

Page 935: ...ing Microengine wait time Table 23 101 is an example for old TPU functions in which there are only simple parameter RAM accesses It does not take into consideration the CDC operation and Microengine to Microengine communication The worst case service time for each channel is CPCR CCR 0 Longest thread number of RAM accesses in longest thread 1 RCR 2 clocks Note that the formula adds 1 RAM accesses ...

Page 936: ... PWM on Channel 0 The following shows how to find the WCL for PWM on channel 0 1 Find the worst case service time for each active channel a Longest thread of PWM is 24 CPU clocks with four RAM accesses PSP Angle Angle Mode Angle Time Mode 76 50 6 3 SM 1 160 21 PPWA Mode 0 Mode 1 Mode 2 Mode 3 44 50 2 44 50 9 10 9 10 1 Assumes one master and one slave For each additional slave a Add 32 clocks and 2...

Page 937: ...ce Using the H M H L H M H time slot sequence map the channels that are granted for each time slot See Figure 23 72 Figure 23 72 Next Servicing for Channel 0 Channel 1 will be serviced in the middle priority time slot before channel 0 is serviced again 3 Add time for the six clock CPU time slot transitions See Figure 23 72 and Table 23 103 A four clock NOP occurs after each channel is serviced sin...

Page 938: ...nel 0 will be serviced twice and channel 2 once before channel 1 is serviced again 3 Add time for the six clock CPU time slot transitions See Figure 23 73 and Table 23 104 131 clocks 25 ns clock 3275 ns Conclusion in this system configuration PPWA can measure a period or pulse of minimum 3275 ns Note that PPWA function optimized for eTPU hardware can use double transition mode to measure very narr...

Page 939: ...minimum of every 6125 ns Note that DIO function optimized for eTPU hardware can use double transition mode to measure two pin transitions at a time and reduce the service time improving the overall system performance and latency 23 5 5 5 Second Pass Worst Case Latency Analysis Following is an example of a second pass analysis for calculating worst case latency for a channel The second pass analysi...

Page 940: ...e perform at the desired level Assign those channels high priority and low channel numbers Try different priority and channel assignments to see how it affects the system 5 The seven slot sequence of H M H L H M H is asymmetrical when put back to back with other seven slot sequences Note that in the following sequence there are two high priority slots next to each other H M H L H M H H M H L H M H...

Page 941: ...l system time The interrupt service routine contains no polling of the parameter RAM Therefore a realistic RCR 0 First Try System Configuration Try a system configuration that seems likely to work If it does not change priority levels or channel numbers The 5 kHz and 50 kHz PWMs are the most time critical functions Those are assigned high priority PPWA is assigned middle priority The DIO is low pe...

Page 942: ...nel 0 Try a different system configuration Second Try System Configuration The second try system configuration is shown in Table 23 107 To find the WCL for channel 0 assume channel 0 has just finished service Map the channels in the H M H L H M H sequence See Figure 23 76 Table 23 107 Second Try System Configuration Channel Priority Function1 2 1 0 RAM collision rate 2 CPU clock rate 40 MHz or 60 ...

Page 943: ...d as shown in Table 23 108 to give channels 0 and 1 a larger margin while still keeping channels 2 8 and 15 within their WCL requirements Table 23 108 Second Try System with Channel 0 and 1 Reconfigured Channel Priority Function1 2 1 0 RAM collision rate 0 High PWM at 50 kHz needs a 10 μs WCL 1 High PWM at 50 kHz needs a 10 μs WCL 2 Middle PWM at 5 kHz needs a 40 μs WCL 8 Low PPWA at 5 kHz needs a...

Page 944: ...annel Timing Figure 23 78 shows the main timings related to microinstruction execution For timings of eTPU block internal interface signals consult the eTPU Integration Guide For timings internal to the eTPU refer to the eTPU Creation Guide 2 CPU clock rate 40 MHz or 60 ns per clock period Table 23 109 Parameter Addresses and Endianness Parameter byte address offset n word address offset big endia...

Page 945: ...TCR1 2 T2 T4 T2 T4 T2 T4 1 microcycle 1 microcycle 1 microcycle tn tn 1 tn 2 tn 1 tn 1 MRL1 2 TDL1 2 CAP1 2 Pin Action due Match uInstr uInstn uInstn 1 uInst Set Pin Pin Action due uInstr Note TCR clock prescaler selection 2 x system clock Updated Pin Value Updated Pin Value uInstr uInstn Pre fetch uInstn 1 uInstn 2 Execution System Clock T4 match on tn 1 ...

Page 946: ...ll state due to an NDEDI queue full see Section 23 4 10 2 Development Support Features for more details T2 and T4 states are defined as microcycle timing states not to be confounded with logic states of one system clock in which the T clocks continue to run but the control signals associated with the clocks are unaffected That is no operation occurs during these states Both T2 and T4 states occur ...

Page 947: ...ntil one of the next T2 clock pulses of another microcycle T4 hold execution in debug mode or stall from clock pulse T4 until one of the next T4 clock pulses of another microcycle Figure 23 80 and Figure 23 81 shows the timing of T2 and T4 timing states respectively Figure 23 80 T2 timing T4 T2 T2 T2 T2 T2 1st 2nd T2 T4 T2 T4 T2 T CLOCKS SYS CLOCK Nth T2 WAIT T2 T4 μPC A1 A2 T4 T4 A2 A3 T2 A1 A0 A...

Page 948: ...1 2 incrementing or EAC tooth sensing TCRCLK in angle mode The synchronizer delay is 2 or 3 system clocks depending on the phase of the synchronizer when the input transition happens The edge detection takes 1 more system clock The total delays are thus Min Total Delay Min Synchronizer Delay Min Filter Delay Edge Detection Delay Min Total Delay 3 Min Filter Delay Max Total Delay Max Synchronizer D...

Page 949: ... Enable Register define ETPUCDTRER_1_OFFSET 0x250 Data TransF Interrupt Enable Register channel0 configuration registers define ETPUC0CR_1_OFFSET 0x400 Channel0 Configuration Register define ETPUC0SCR_1_OFFSET 0x404 Channel0 Status Control Register define ETPUC0HSRR_1_OFFSET 0x408 Channel0 Host Service Req Register channel1 configuration registers define ETPUC1CR_1_OFFSET 0x410 Channel1 Configurat...

Page 950: ...7 define ENTRY_TABLE_BASE x x 0x1F ETPUMCR fields Module Configuration Register define PSE 0x00000002 Parameter sign extension define SCMMISEN 0x00000200 SCM MISC enable define VIS 0x00000040 SCM visibility define GTBE 0x00000001 Global time base enable ETPUTBCR_1 fields Time Base Configuration Register define TCRCLK_FILTER_TWOSAMPLE 0x00000000 TCRCLK filter in Two sample mode define TCRCLK_FILTER...

Page 951: ...EL_PARAM_BASE_ADDR 0x00 ETPUC1CR_1 CHANNEL_INT_ENABLE CHANNEL_FUNCTION 15 CHANNEL_PARAM_BASE_ADDR 0x02 Write to the channel status control registers ETPUCxSCR to choose variations within the function flow ETPUC0SCR_1 FUNCTION_MODE 0 no parity for transmitter ETPUC1SCR_1 FUNCTION_MODE 0 no parity for receiver write to spram for parameter initialization of each configured channel MATCH_RATE_TX MATCH...

Page 952: ...nables in column head specifies which other events are enabled or disabled Initially disabled events specified in initially blocked column are usually enabled by other events In double transition submodes the first transition detected is always considered trans1 and the second is considered trans2 This means that trans1 event actually enables the detection of trans2 event This is not explicit in t...

Page 953: ...atch 2 2 match 2 none 2 trans 1 match 1 1 trans 2 match2 2 trans 1 match 1 1 match 2 none 2 trans 2 none 2 trans 2 match 2 2 em_b_st none match 1 match 2 both trans 1 matches both trans 2 none 2 match 2 match 1 both trans 1 matches both trans 2 none 2 em_b_dt none match 1 match 2 both trans 1 none 1 trans 2 none 2 match 2 match 1 both trans 1 match 1 1 match 2 none 2 trans 2 none 2 trans 2 match 2...

Page 954: ...none 1 trans 2 match 2 2 match 2 trans 2 2 match 2 trans 1 2 sm_st2 match 2 match 1 none both trans 1 none both trans 2 none 2 trans 1 match 1 both trans 2 none 2 sm_dt match 2 match 1 none both trans 1 none 1 trans 2 none 2 trans 1 none 1 match 1 none 2 trans 2 none 2 trans 1 none 1 trans 2 match1 2 sm_st_e3 match 2 trans 2 match 1 none 1 trans 1 none 1 trans 1 match 1 1 Generates Service Request...

Page 955: ... code that calculates the MISC signature for a given array of data based on the previous algorithm define SCM_size MAX_SCM_ADDRESS 4 last byte address converted to 32 bit word define POLY 0x80400007 G x 1 x1 x2 x22 x31 FUNCTION void calc_misc PURPOSE This function calculates the MISC value INPUTS NOTES none RETURNS NOTES MISC value GENERAL NOTES the array unsigned int data represents the actual me...

Page 956: ...la Average MISC period S 4 f 1 L where f is clock frequency S is SCM size in bytes and L is eTPU load as a percentage of execution clocks over a period of time including TST clocks Further detail on MISC calculation can be found on Section 23 4 10 3 1 SCM Test Multiple Input Signature Calculator The application note AN2192 Detecting Errors in the Dual Port RAM DPTRAM Module is also a good source o...

Page 957: ...FUFx and TORFx assuming that all interrupts are enabled 24 1 2 Device Specific Pin Configuration Features The following eQADC pins are multiplexed and configuration of the corresponding Systems Integration Unit SIU registers is necessary 24 1 2 1 AN12 MA0 SDS These pins are configured by setting the Pad Configuration Register 215 SIU_PCR215 on the SIU NOTE Attempts to convert the input voltage app...

Page 958: ...r SIU_ETISR on the SIU 24 2 Introduction 24 2 1 Module Overview The Enhanced Queued Analog to Digital Converter EQADC block provides accurate and fast conversions for a wide range of applications The EQADC provides a parallel interface to two on chip analog to digital converters ADCs a single master to single slave serial interface to an off chip external device and a parallel side interface to on...

Page 959: ...ach with 4 entries 1 Companion modules can be DSP modules or any other processing block AN8 ANW AN9 ANX TBIAS AN10 ANY AN11 ANZ AN0 DAN0 AN1 DAN0 AN2 DAN1 AN3 DAN1 AN4 DAN2 AN5 DAN2 AN6 DAN3 AN7 DAN3 Priority Decoder External Device SDS FCK SDO SDI MUX 40 1 ADC0 ADC1 MUX 40 1 BIAS GEN REFBYPC CFIFOx NOTE x 0 1 2 3 4 5 32 bits CQueue y RQueue y System RFIFOx 16 bits CBuffer0 CBuffer1 EQADC FIFO Con...

Page 960: ...for a full duplex synchronous parallel communication between the EQADC and several on chip companion modules Figure 24 1 also depicts data flow through the EQADC Commands are contained in system memory in a user defined data structure The most likely data structure to be used is a queue as depicted in the Figure 24 11 Command data is moved from the command queue CQueue to the CFIFOs by either the ...

Page 961: ...rence voltages 25 VREF and 75 VREF for ADC calibration purposes 40 input channels available to the two on chip ADCs 4 pairs of differential analog input channels Full duplex synchronous serial interface to an external device Has a free running clock for use by the external device Supports a 26 bit message length Transmits a null message when there are no triggered CFIFOs with commands bound for ex...

Page 962: ...he CFIFO0 delivers commands to the ADC as before but those commands are not invalidated after they are sent in fact they are invalidated only because the Transfer Next Data Pointer has moved on When it encounters these repeated commands the CFIFO0 only fills once using the DMA as usual until either it is full or a command with End of Queue is encountered Thereafter the sub queue repeats wraps The ...

Page 963: ...op after all on chip ADCs cease executing commands When exiting debug mode the EQADC relies on the CFIFO operation modes and on the CFIFO status to determine the next command entry to transfer The EQADC internal behavior after the debug mode entry request is detected differs depending on the status of command transfers No command transfer is in progress The EQADC immediately halts future command t...

Page 964: ...since no scheme is implemented to write protect registers during stop mode If at the time the stop mode entry request is detected there are commands in the on chip CBuffers that were already under execution these commands will be completed but the generated results if any will not be sent to the RFIFOs until stop mode is exited Commands whose execution has not started will not be executed until st...

Page 965: ... The message of the CFIFO that caused the abort of the previous serial transmission will only be transmitted after stop mode is exited Command Null message transfer through serial interface was aborted but next serial transmission did not start If the stop mode entry request is detected between the time a previous serial transmission was aborted and the start of the next transmission the EQADC wil...

Page 966: ...TVRLI Input Single ended analog input Single ended analog input from external multiplexers Test IR drop on VRL Analog AN11 ANZ TVRHI Input Single ended analog input Single ended analog input from external multiplexers Test IR drop on VRH Analog AN12 T50PVREF Input Output Single ended analog input Test 50 VREF1 analog output Analog AN13 T25PVREF Input Output Single ended analog input Test 25 VREF1 ...

Page 967: ...g INA_ADC1_0 9 Input Single ended analog input Analog MA0 Output External multiplexer control signal 0 Digital MA1 Output External multiplexer control signal 0 Digital MA2 Output External multiplexer control signal 0 Digital FCK Output EQADC SSI free running clock 0 Digital SDS Output EQADC SSI serial data select 1 Digital SDI Input EQADC SSI serial data in Digital SDO Output EQADC SSI serial data...

Page 968: ...e terminal of the differential analog input DAN1 DAN1 DAN1 24 4 2 4 AN3 DAN1 Single ended analog input Differential analog input negative terminal AN3 is a single ended analog input to the two on chip ADCs DAN1 is the negative terminal of the differential analog input DAN1 DAN1 DAN1 24 4 2 5 AN4 DAN2 Single ended analog input Differential analog input positive terminal AN4 is a single ended analog...

Page 969: ...t to one of the on chip ADCs in external multiplexed mode TBIAS is used during factory test to verify the bias generator circuit 24 4 2 11 AN10 ANY Single ended analog input Single ended analog input from external multiplexers AN10 is a single ended analog input to the two on chip ADCs ANY is a single ended analog input to one of the on chip ADCs in external multiplexed mode 24 4 2 12 AN11 ANZ Sin...

Page 970: ...ed form a select signal associated with external multiplexers 24 4 2 20 FCK EQADC SSI free running clock FCK is a free running clock signal for synchronizing transmissions between the EQADC master and the external slave device 24 4 2 21 SDS EQADC SSI serial data select SDS is the serial data select output It is used to indicate to the external slave device when it can latch incoming serial data wh...

Page 971: ...s of the memory map is undefined 24 5 1 EQADC Memory Map This section provides memory maps for the EQADC block Table 24 2 EQADC Memory Map Address Use Access EQADC_BASE 0x000 EQADC Module Configuration Register EQADC_MCR Unrestricted EQADC_BASE 0x004 EQADC Test Register EQADC_TST Test EQADC_BASE 0x008 EQADC Null Message Send Format Register EQADC_NMSFR Unrestricted EQADC_BASE 0x00C EQADC External ...

Page 972: ...5 Unrestricted EQADC_BASE 0x088 Reserved EQADC_BASE 0x08C Reserved EQADC_BASE 0x090 EQADC CFIFO Transfer Counter Register 0 EQADC_CFTCR0 Unrestricted EQADC_BASE 0x094 EQADC CFIFO Transfer Counter Register 1 EQADC_CFTCR1 Unrestricted EQADC_BASE 0x098 EQADC CFIFO Transfer Counter Register 2 EQADC_CFTCR2 Unrestricted EQADC_BASE 0x09C Reserved EQADC_BASE 0x0A0 EQADC CFIFO Status Snapshot Register 0 EQ...

Page 973: ... EQADC CFIFO5 Registers EQADC_CF5Rw w 0 3 Read only EQADC_BASE 0x250 EQADC_BASE 0x2FC Reserved EQADC_BASE 0x300 EQADC_BASE 0x30C EQADC RFIFO0 Registers EQADC_RF0Rw w 0 3 Read only EQADC_BASE 0x310 EQADC_BASE 0x33C Reserved EQADC_BASE 0x340 EQADC_BASE 0x34C EQADC RFIFO1 Registers EQADC_RF1Rw w 0 3 Read only EQADC_BASE 0x350 EQADC_BASE 0x37C Reserved EQADC_BASE 0x380 EQADC_BASE 0x38C EQADC RFIFO2 Re...

Page 974: ... the abort of that transmission NOTE When disabling the EQADC SSI the FCK will not stop until it reaches its low phase DBG 0 1 Debug enable The DBG field defines the EQADC response to a debug mode entry request as in Table 24 4 Register address EQADC_BASE 0x000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24...

Page 975: ...R defines the format of the null message sent to the external device Figure 24 4 EQADC Null Message Send Format Register EQADC_NMSFR 0b11 Enter debug mode If the EQADC SSI is enabled FCK is free running while the EQADC is in debug mode Register address EQADC_BASE 0x004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 ...

Page 976: ...d on the receive data Refer to page 1022 for more information on the MESSAGE_TAG field NOTE Writing to the EQADC Null Message Send Format Register while the serial transmissions are enabled ESSIE field configured to 0b11 in Section 24 5 2 1 EQADC Module Configuration Register EQADC_MCR is not recommended 24 5 2 4 EQADC External Trigger Digital Filter Register EQADC_ETDFR The EQADC External Trigger...

Page 977: ...ital filter is bypassed by using the input control the DFL is not considered and the trigger input signal is not filtered 24 5 2 5 EQADC CFIFO Push Registers EQADC_CFPR The EQADC CFIFO Push Registers EQADC_CFPR provide a mechanism to fill the CFIFOs with command messages from the CQueues Refer to Section 24 6 4 EQADC Command FIFOs for more information on the CFIFOs and to Section 24 6 2 3 Message ...

Page 978: ...ting half words or bytes to EQADC_CFPR will still push the whole 32 bit CF_PUSH field into the corresponding CFIFO but undefined data will fill the areas of CF_PUSH that were not specifically designated as target locations for the write 24 5 2 6 EQADC Result FIFO Pop Registers EQADC_RFPR The EQADC Result FIFO Pop Registers EQADC_RFPR provide a mechanism to retrieve data from RFIFOs Register addres...

Page 979: ...contain bits that affect CFIFOs These bits specify the CFIFO operation mode and can invalidate all of the CFIFO contents Figure 24 8 EQADC CFIFO Control Register 0 EQADC_CFCR0 Register address EQADC_BASE 0x030 Register address EQADC_BASE 0x034 Register address EQADC_BASE 0x038 Register address EQADC_BASE 0x03C Register address EQADC_BASE 0x040 Register address EQADC_BASE 0x044 0 1 2 3 4 5 6 7 8 9 ...

Page 980: ...mode of operation of CFIFO0 In this case it is possible to repeat some sequence of commands of this FIFO For more details refer to Section 24 6 4 2 CFIFO0 Streaming Mode Description 1 Enable the streaming mode of CFIFO0 0 Streaming mode of CFIFO0 is disabled Register address EQADC_BASE 0x054 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 MODE2 0 0 0 0 W SSE 2 CFIN V2 RESET 0 0 0 0 0 0 0 0...

Page 981: ...ad as 0 Writing a 0 has no effect 1 Invalidate all of the entries in the corresponding CFIFO 0 No effect NOTE Writing CFINVx only invalidates commands stored in CFIFOx previously transferred commands that are waiting for execution that is commands stored in the CBuffers will still be executed and results generated by them will be stored in the appropriate RFIFO NOTE CFINVx must not be written unle...

Page 982: ... bits to enable the generation of interrupt or DMA requests when the corresponding flag bits are set in Section 24 5 2 9 EQADC FIFO and Interrupt Status Registers EQADC_FISR 0b1001 Software Trigger Continuous Scan 0b1010 Low Level Gated External Trigger Continuous Scan 0b1011 High Level Gated External Trigger Continuous Scan 0b1100 Falling Edge External Trigger Continuous Scan 0b1101 Rising Edge E...

Page 983: ... 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R NCIE 1 TORI E1 PIE1 EOQ IE1 CFUI E1 0 CFF E1 CFF S1 0 0 0 0 RFOI E1 0 RFD E1 RFD S1 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Register address EQADC_BASE 0x064 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R NCIE 2 TORI E2 PIE2 EOQ IE2 CFUI E2 0 CFF E2 CFF S2 0 0 0 0 RFOI E2 0 RFD E2 RFD S2 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 984: ...of Queue Interrupt Enable x EOQIEx enables the EQADC to generate an interrupt request when the corresponding EOQFx in Section 24 5 2 9 EQADC FIFO and Interrupt Status Registers EQADC_FISR is asserted 1 Enable End of Queue interrupt request 0 Disable End of Queue interrupt request CFUIEx CFIFO Underflow Interrupt Enable x CFUIEx enables the EQADC to generate an interrupt request when the correspond...

Page 985: ...Command FIFO Trigger Overrun Interrupt requests of ALL CFIFOs are ORed When RFOIEx CFUIEx and TORIEx are all asserted this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted RFOFx CFUFx and TORFx assuming that all interrupts are enabled See Section 24 6 8 EQADC DMA Interrupt Request for details 1 Enable Overflow Interrupt request 0 Disable Overflow Inter...

Page 986: ...or level trigger mode Trigger overrun occurs when an already triggered CFIFO receives an additional trigger When TORIEx in Section 24 5 2 8 EQADC Interrupt and DMA Control Registers EQADC_IDCR and TORFx are asserted an interrupt request will be generated Apart from generating an independent interrupt request for a CFIFOx Trigger Overrun event the EQADC also provides a combined interrupt at which t...

Page 987: ...l transmission of the entry is completed In software trigger mode PFx will never become asserted If PIEx in Section 24 5 2 8 EQADC Interrupt and DMA Control Registers EQADC_IDCR and PFx are asserted an interrupt will be generated Write 1 to clear the PFx Writing a 0 has no effect Refer to Section 24 6 4 7 3 Pause Status for more information on the Pause Flag 1 Entry with asserted PAUSE bit was tra...

Page 988: ...rupt request for a CFIFOx underflow event the EQADC also provides a combined interrupt at which the Result FIFO Overflow Interrupt the Command FIFO Underflow Interrupt and the Command FIFO Trigger Overrun Interrupt requests of ALL CFIFOs are ORed When RFOIEx CFUIEx and TORIEx are all asserted this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted RFOFx ...

Page 989: ...w data will be ignored When RFOIEx in Section 24 5 2 8 EQADC Interrupt and DMA Control Registers EQADC_IDCR and RFOFx are both asserted the EQADC generates an interrupt request Apart from generating an independent interrupt request for an RFIFOx overflow event the EQADC also provides a combined interrupt at which the Result FIFO Overflow Interrupt the Command FIFO Underflow Interrupt and the Comma...

Page 990: ...TRx is wrapped to zero else it is incremented by one For details refer to Section 24 6 4 1 CFIFO Basic Functionality Writing any value to TNXTPTRx has no effect RFCTRx 0 3 RFIFOx Entry Counter RFCTRx indicates the number of data items stored in the RFIFOx When the EQADC stores a piece of new data into RFIFOx it increments RFCTRx by one Reading the whole word half word or any bytes of the correspon...

Page 991: ...n of the entry is completed The EQADC increments the TC_CFx value by Register address EQADC_BASE 0x090 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 TC_CF0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 TC_CF1 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Register address EQADC_BASE 0x094 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1...

Page 992: ...he internal external CBuffers EQADC_CFSSR0 1 are related to the on chip CBuffers CBuffer0 1 while EQADC_CFSSR2 is related to the external CBuffers All fields of a particular EQADC_CFSSR register are captured at the beginning of a command transfer to the CBuffer associated with that register Note that captured status register values are associated with previous command transfer This means that the ...

Page 993: ...12 13 14 15 R CFS0_TCB 1 CFS1_TCB 1 CFS2_TCB 1 CFS3_TCB 1 CFS4_TCB 1 CFS5_TCB 1 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 LCFTCB1 TC_LCFTCB1 W RESET 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Register address EQADC_BASE 0x0A8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFS0_TSSI CFS1_TSSI CFS2_TSSI CFS3_TSSI CFS4_TSSI CFS5_TSSI 0...

Page 994: ...d was transferred to CBuffer2 LCFTSSI 0 3 Last CFIFO to Transfer Commands through the EQADC SSI LCFTSSI holds the CFIFO number to have completed a previous command transfer to an external CBuffer through the EQADC SSI LCFTSSI does not indicate the transmission of null messages TC_LCFSSI 0 10 Transfer Counter for Last CFIFO to Transfer commands through EQADC SSI TC_LCFTSSI indicates the number of c...

Page 995: ...1 CFS2 CFS3 CFS4 CFS5 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 24 10 Current CFIFO Status CFIFO Status Field Value Explanation IDLE 0b00 CFIFO is disabled CFIFO is in single scan edge or level trigger mode and does not have SSS asserted EQ...

Page 996: ...odule Configuration Register EQADC_MCR BR 0 3 Baud Rate Field The BR field selects system clock divide factor as shown in Table 24 12 The baud clock is calculated by dividing the system clock by the clock divide factor specified with the BR field NOTE The BR field must only be written when the EQADC SSI is disabled See ESSIE field in Section 24 5 2 1 EQADC Module Configuration Register EQADC_MCR R...

Page 997: ...d Writes have no effect 1 Receive data is valid 0 Receive data is not valid Table 24 12 System Clock Divide Factor for Baud Clock BR 0 3 System Clock Divide Factor 1 1 If the system clock is divided by a odd number then the serial clock will have a duty cycle different from 50 0b0000 2 0b0001 3 0b0010 4 0b0011 5 0b0100 6 0b0101 7 0b0110 8 0b0111 9 0b1000 10 0b1001 11 0b1010 12 0b1011 13 0b1100 14 ...

Page 998: ...formation on CFIFOs These registers are read only Data written to these registers is ignored Figure 24 24 EQADC CFIFO0 Registers EQADC_CF0Rw w 0 3 Figure 24 25 EQADC CFIFO1 Registers EQADC_CF1Rw w 0 3 Register address EQADC_BASE 0x100 Register address EQADC_BASE 0x104 Register address EQADC_BASE 0x108 Register address EQADC_BASE 0x10C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFIFO0_DATAw W RESET 0 ...

Page 999: ..._BASE 0x18C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFIFO2_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CFIFO2_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register address EQADC_BASE 0x1C0 Register address EQADC_BASE 0x1C4 Register address EQADC_BASE 0x1C8 Register address EQADC_BASE 0x1CC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFIFO3_DATAw W R...

Page 1000: ...re uniquely mapped to its four 32 bit entries Refer to Section 24 6 4 EQADC Command FIFOs for more information on CFIFOs These registers are read only Data written to these registers is ignored CFIFOx_DATAw 0 31 CFIFOx Data w w 0 3 Register address EQADC_BASE 0x200 Register address EQADC_BASE 0x204 Register address EQADC_BASE 0x208 Register address EQADC_BASE 0x20C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 ...

Page 1001: ...C Result FIFOs for more information on RFIFOs These registers are read only Data written to these registers is ignored Figure 24 31 EQADC RFIFO0 Registers EQADC_RF0Rw w 0 3 Register address EQADC_BASE 0x110 Register address EQADC_BASE 0x114 Register address EQADC_BASE 0x118 Register address EQADC_BASE 0x11C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFIFO0_EDATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1002: ... 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RFIFO1_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register address EQADC_BASE 0x380 Register address EQADC_BASE 0x384 Register address EQADC_BASE 0x388 Register address EQADC_BASE 0x38C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 ...

Page 1003: ... 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RFIFO3_DATAw W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register address EQADC_BASE 0x400 Register address EQADC_BASE 0x404 Register address EQADC_BASE 0x408 Register address EQADC_BASE 0x40C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 ...

Page 1004: ... configurations commands bound for the on chip ADCs These are half word addresses Further the following restrictions apply when accessing these registers Registers ADC0_CR ADC0_GCCR ADC0_OCCR ADC0_AGR and ADC0_AOR can only be accessed by configuration commands sent to CBuffer0 Registers ADC1_CR ADC1_GCCR ADC1_OCCR ADC1_AGR and ADC1_AOR can only be accessed by configuration commands sent to CBuffer...

Page 1005: ...d Format for Alternate Configurations Write 0x0C ADC0 ADC1 Conversion Command for Alternate Configuration 5 See Section Conversion Command Format for Alternate Configurations Write 0x0D ADC0 ADC1 Conversion Command for Alternate Configuration 6 See Section Conversion Command Format for Alternate Configurations Write 0x0E ADC0 ADC1 Conversion Command for Alternate Configuration 7 See Section Conver...

Page 1006: ... Control Register ADC_ACR7 Write Read 0x49 Reserved 0x4A Reserved 0x4B Reserved 0x4C Alternate Configuration 8 Control Register ADC_ACR8 Write Read 0x4D 0x6F Reserved 0x70 Pull Up Down Control Register0 ADC_PUDCR0 Write Read 0x71 Pull Up Down Control Register0 ADC_PUDCR1 Write Read 0x72 Pull Up Down Control Register0 ADC_PUDCR2 Write Read 0x73 Pull Up Down Control Register0 ADC_PUDCR3 Write Read 0...

Page 1007: ...description about how ADC0 1_EMUX affects channel number decoding 1 External multiplexer enabled external multiplexer channels can be selected 0 External multiplexer disabled no external multiplexer channels can be selected NOTE Both ADC0 1_EMUX bits must not be asserted at the same time NOTE The ADC0 1_EMUX bit must only be written when the ADC0 1_EN bit is negated ADC0 1_EMUX can be set during t...

Page 1008: ... 1 clock as in Table 24 14 See Section 24 6 6 2 ADC Clock and Conversion Speed on page 1066 for details about how to set ADC0 1_CLK_PS NOTE The ADC0 1_CLK_PS field must only be written when the ADC0 1_EN bit is negated This field can be configured during the same write cycle used to set ADC0 1_EN Table 24 14 System Clock Divide Factor for ADC Clock ADC0 1_CLK_PS 0 4 System Clock Divide Factor 0b00...

Page 1009: ...S 0 3 Time Base Counter Clock Prescaler The TBC_CLK_PS field contains the system clock divide factor for the time base counter It controls the accuracy of the time stamp The prescaler is disabled when TBC_CLK_PS is set to 0b0000 0b11010 54 0b11011 56 0b11100 58 0b11101 60 0b11110 62 0b11111 64 ADC0 1 Register address 0x02 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 TBC_CLK_PS W...

Page 1010: ...15 Time Base Counter VALUE Field The TBC_VALUE field contains the current value of the time base counter Reading TBC_VALUE returns the current value of time base counter Writes to TBC_VALUE register load the written data to the counter The time base counter counts from 0x0000 to 0xFFFF and wraps when reaching 0xFFFF 24 5 3 4 ADC0 1 Gain Calibration Constant Registers ADC0_GCCR and ADC1_GCCR The AD...

Page 1011: ...nversion results The offset constant is a signed 14 bit integer value Refer to Section 24 6 6 6 ADC Calibration Feature for details about the calibration scheme used in the EQADC OCC0 1 0 13 Offset Calibration Constant of ADC0 1 OCC0 1 contains the offset calibration constant used to fine tune ADC0 1 conversion results Negative values should be expressed using the two s complement representation A...

Page 1012: ... this bit is useful for sending the result of the ADC to the STAC bus master but not putting the result in the result queue 1 No result transfer to result queue Decimation Filter PRE FILL mode 0 Result transfer to result queue Decimation Filter in filtering mode DEST 0 3 Conversion Result Destination Selection The DEST 0 3 field selects the destination of the conversion result generated by the Alt...

Page 1013: ...DC0_AGR1 2 and ADC1_AGR1 2 The Alternate Gain Registers ADC0_AGRx and ADC1_AGRx x 1 2 contain the gain calibration constants used to fine tune the ADCs conversion results for alternate configurations 1 or 2 A conversion from an ADC uses the corresponding ADC0_AGRx or ADC1_AGRx register when the conversion command with the alternate configuration format is written to an address in the range 0x08 0x...

Page 1014: ...e for details about the calibration scheme used in the EQADC ALTOCC0 1x 0 13 Alternate Offset Calibration Constant ALTOCC0 1x 0 13 contain the offset calibration constants used to fine tune ADCs conversion results for alternate configurations 1 or 2 Negative values should be expressed using the two s complement representation 24 5 3 9 ADC Pull Up Down Control Register x ADC_PUDCRx x 0 7 The ADC Pu...

Page 1015: ...ated by the EQADC The EQADC supports software and hardware triggers from other blocks or external pins to initiate transfers of commands from the multiple CFIFOs to the on chip ADCs or to the external device ADC0 1 Register address 0x70 0x77 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 CH_PULLx 0 0 PULL_STR x 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 2...

Page 1016: ...ain as soon as the critical timing commands have been finished The multiple Result FIFOs RFIFOs can receive data from the on chip ADCs from an off chip external device or from an on chip companion module Data from the on chip ADCs can be routed to the side interface processed by the on chip companion module and then routed back through the side interface to the RFIFOs 24 6 2 Data Flow in EQADC 24 ...

Page 1017: ... all incoming results to be shaped in a predefined Result Message format Figure 24 47 shows how result data flows inside the EQADC system Results generated on the on chip ADCs are adjusted considering the selected resolution of the ADC and are formatted into result messages inside the Result Format and Calibration Sub Block This result message can be routed directly to one of the RFIFOs or to an o...

Page 1018: ...n RFIFO can occur simultaneously Figure 24 47 Result Flow during EQADC operation 24 6 2 2 Assumptions Requirements Regarding the External Device The external device exchanges command and result data with the EQADC through the EQADC SSI interface This section explains the minimum requirements an external device has to meet to properly interface with the EQADC Some assumptions about the architecture...

Page 1019: ...hould be executed in that order they were received Results generated by the execution of commands of a CBuffer should be returned in the order the CBuffer received these commands 24 6 2 2 4 Null and Result Messages The external device must be capable of correctly processing null messages as specified in the Section 24 5 2 3 EQADC Null Message Send Format Register EQADC_NMSFR In case no valid resul...

Page 1020: ...ce Operation Apart from the BN bit the ADC Command of a command message can be formatted to communicate to an arbitrary external device provided that the device returns an RFIFO header in the format expected by the EQADC When the FIFO Control Unit receives return data message it decodes the message tag field and stores the 16 bit data into the corresponding RFIFO Conversion Command Format for the ...

Page 1021: ...re asserted in the same command message the respective flags are set but the CFIFO status changes as if only the EOQ bit were asserted REP Repeat loop Start Point Indication Bit The REP bit is asserted in the command to indicate where is the start point of the sub queue to be repeated when the streaming mode is enabled The PAUSE bit indicates the end point of the sub queue Therefore both can occur...

Page 1022: ...e Section 24 6 6 3 Time Stamp Feature for details 1 Return conversion time stamp after the conversion result 0 Return conversion result only FMT Conversion Data Format FMT specifies to the EQADC how to format the 12 bit conversion data returned by the ADCs into the 16 bit format which is sent to the RFIFOs See Section ADC Result Format for On Chip ADC Operation for details Table 24 21 MESSAGE_TAG ...

Page 1023: ...e conversion result A time stamp information can be optionally requested All fields except FFMT and ALT_CONFIG_SEL are identical to the ones in the standard configuration format Only the fields which are different from the standard format will be described here Figure 24 49 Conversion Command Format for Alternate Configurations FFMT Flush or Format The function of this bit depends on the DEST fiel...

Page 1024: ...of the on chip ADCs No conversion data will be returned for a write configuration command Write configuration commands are differentiated from read configuration commands by a negated R W bit Figure 24 50 Write Configuration Command Format for On Chip ADC Operation EOQ End Of Queue Bit PAUSE Pause Bit REP Repeat loop Start Point Indication Bit EB External Buffer Bit BN Buffer Number Bit Refer to S...

Page 1025: ...igure 24 51 describes the command message format for a read configuration command when interfacing with the on chip ADCs A read configuration command is used to read the contents of the on chip ADC registers which are only accessible via command messages Read configuration commands are differentiated from write configuration commands by an asserted R W bit Figure 24 51 Read Configuration Command F...

Page 1026: ...0 or 12 bit data received from the ADC The resolution adjustment consists of changing the conversion result input from 8 10 or 12 bits right aligned to a 12 bit word left aligned refer to Section 24 6 6 5 ADC Resolution Selection Feature for details When the CAL bit is asserted this 14 bit data is the result of the calculations performed in the EQADC MAC unit using the 12 bit data result of the re...

Page 1027: ...press negative values 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 RESOLUTION ADJUSTED CONVERSION_RESULT ADC Result Table 24 24 Correspondence between analog voltages and digital values1 2 Voltage Level on Channel V Corresponding 8 bit Conversion Result Returned by the ADC Corresponding 10 bit Conversion Result Returned by the ADC Corresponding 12 bit Conversion Result Returned by the ADC 16 bit Resu...

Page 1028: ...d be sent The remaining 25 bits can be anything decodable by the external device Only the ADC Command portion of a command message is transferred to the external device Differential Conversion s 2 56 0xFFF 0x3FFC 0x1FFC 0x3FF 0x3FF0 0x1FF0 0xFF 0x3FC0 0x1FC0 2 56 LSB 0xFFF 0x3FFC 0x1FFC 0x3FF 0x3FF0 0x1FF0 0xFF 0x3FC0 0x1FC0 0 0x800 0x2000 0x0000 0x200 0x2000 0x0000 0x80 0x2000 0x0000 2 56 LSB 0x0...

Page 1029: ...ND 0 24 OFF CHIP COMMAND Field The OFF_CHIP_COMMAND field can be anything decodable by the external device It is 25 bits long and it is transferred together with the BN bit to the external device when the CFIFO is triggered Refer to Section Conversion Command Format for the Standard Configuration for a description of the command message used when interfacing with the on chip ADCs Result Message Fo...

Page 1030: ... entries in a external CBuffer for example NOTE After reset the EQADC always assumes that the external CBuffers are full and cannot receive commands ADC_RESULT 0 15 ADC RESULT Field ADC_RESULT is the result data received from the external device or on chip ADC This can be the result of a conversion command data requested via a read configuration command or time stamp value The ADC_RESULT of any in...

Page 1031: ...the null message send format of the external device Figure 24 57 illustrates the null message receive format It has the same fields found in a Result Message with the exception that the ADC result is not used Refer to Section Result Message Format for External Device Operation for more information The MESSAGE_TAG field must be set to the Null Message tag 0b1000 The EQADC does not store into an RFI...

Page 1032: ... CQueues in the system memory When a CFIFO is not full the EQADC sets the corresponding CFFF bit in Section 24 5 2 9 EQADC FIFO and Interrupt Status Registers EQADC_FISR If CFFE is asserted in Section 24 5 2 8 EQADC Interrupt and DMA Control Registers EQADC_IDCR the EQADC generates requests for more commands from a CQueue An interrupt request served by the host CPU is generated when CFFS is negate...

Page 1033: ...tion When CFSx in Section 24 5 2 12 EQADC CFIFO Status Register EQADC_CFSR is TRIGGERED the EQADC generates the proper control signals for the transfer of the entry pointed by Transfer Next Data Pointer CFUFx in Section 24 5 2 9 EQADC FIFO and Interrupt Status Registers EQADC_FISR is set when a CFIFOx underflow event occurs A CFIFO underflow occurs when the CFIFO is in TRIGGERED state and it becom...

Page 1034: ...plementation has only four entries In this example CFIFOx with 16 entries is shown in sequence after pushing and transferring entries 32 bit Entry 1 32 bit Entry 2 Push Next Data Pointer Transfer Next Data Pointer CFIFO Push Register Write to CFIFO Control Logic DMA Done Interrupt DMA Request Control Signals SkyBlue Line interface by CPU or DMA Data to external device or to on chip ADCs Transfer C...

Page 1035: ... Push Transfer CFIFOx First In After reset or invalidation Next Data Pointer Next Data Pointer Last In Valid Entry Empty Entry Push Transfer CFIFOx Some entries pushed but none Executed Next Data Pointer Next Data Pointer Transfer CFIFOx No entries pushed but some executed Next Data Pointer First In Last In Push Next Data Pointer Push CFIFOx Entries pushed until full and none executed Next Data Po...

Page 1036: ...completed then the queue stops and enters the Pause state waiting for a trigger This is the same as normal behavior The Pause state is exited in one of two ways Repeat Trigger or Repeat Trigger with Advance Trigger The Repeat trigger with no Advance trigger causes the Transfer Next Data Pointer to be loaded with the Repeat Pointer location and CCWs are then executed from the Repeat Pointer back to...

Page 1037: ...starting a new loop In this case outside a loop if a PAUSE bit is decoded this means to disable the Repeat trigger detector This can be useful if the Repeat trigger is not required for some interval of time The Repeat trigger detector is enabled again when the next Advance trigger event is detected 24 6 4 2 3 CFIFO0 Diagram Description in Streaming Mode Figure 24 60 represents the main components ...

Page 1038: ...FIFO with 16 entries is shown for clarity of explanation the actual hardware implementation has only four eight entries In this example CFIFO0 with 16 entries is shown in sequence after pushing and transferring entries 32 bit Entry 1 32 bit Entry 2 Push Next Data Pointer Transfer Next Data Pointer CFIFO Push Register Write to CFIFO Control Logic DMA Done Interrupt DMA Request Control Signals SkyBl...

Page 1039: ...Transitory state Repeat trigger with no Entries pushed but not Repeat Pause Repeat Pointer Repeat Pause up to pause bit waiting for trigger Repeat Pause Repeat Pointer Transfer CFIFO0 Next Data Pointer Last In Push Next Data Pointer Repeat Pause Repeat Pointer Advance trigger causes loop execution Transfer CFIFO0 Next Data Pointer Last In Push Next Data Pointer Repeat Pause Repeat Pointer Transito...

Page 1040: ...bit EOQ continues to operate as in normal mode unless the Repeat mode is enabled In this case the Pause bit takes presidence and a Repeat trigger causes the jump back described A Repeat trigger with Advance trigger causes the queue to end Another error condition occur when the repeat trigger is in the TRIGGERED state and a new repeat trigger is received In this case a trigger overflow occurs but t...

Page 1041: ...d by decoding the EB and BN bits in the command message see Section 24 6 2 3 Message Format in EQADC for details NOTE Triggered but empty CFIFOs underflowing CFIFOs are not considered for prioritization No data from these CFIFOs will be sent to the CBuffers and nor will they stop lower priority CFIFOs from transferring commands Whenever CBuffer0 is able to receive new entries the prioritization su...

Page 1042: ...out The command from the CFIFO is then written into EQADC SSI transmit buffer allowing for a new serial transmission to initiate In case a command is being transmitted the serial transmission is aborted when all following conditions are met CFIFO0 is in TRIGGERED state is not underflowing and its current command is bound for an external CBuffer that is not full the ABORT_ST bit of the command to b...

Page 1043: ...f the previously scheduled data was a null message The time during which SDS is negated is stretched in order to allow the EQADC to load that command and start its transmission However if the previously scheduled data was a command no rescheduling occurs and the next transmission starts without delays If a CFIFO becomes TRIGGERED while SDS is negated but the EQADC only attempts to reschedule that ...

Page 1044: ...FIFO0 is the only one that can be enabled to abort conversions CFIFO3 External Device Command CFIFO4 Command CFIFO5 Command CFIFO0 Command CFIFO1 Command CFIFO2 Command ADC1 CBuffer1 ADC0 ADC3 CBuffer3 ADC2 CBuffer2 External Device SSI Interface EQADC SSI for CBuffer0 Prioritization 6 x Command Serial Link Command Transmit Buffer 2 entries Command Command Command Command EQADC Prioritization Logic...

Page 1045: ...mum number of system clocks that the ETRIG0 5 signals must be held at a logic level to be recognized as valid All ETRIG signals are filtered A counter for each queue trigger is implemented to detect a transition between logic levels The counter counts at the system clock rate The corresponding counter is cleared and restarted each time the signal transitions between logic levels When the correspon...

Page 1046: ...igger events after an asserted EOQ is detected In continuous scan mode the whole CQueue is scanned multiple times The EQADC also supports different triggering mechanisms for each scan mode The EQADC will not transfer commands from a CFIFO until the CFIFO is triggered The combination of scan modes and triggering mechanisms allows the support of different requirements for scanning input channels The...

Page 1047: ...already shifted out the EQADC will complete the transfer update TC_CF and then switch CFIFO status to IDLE The CFIFOs are not invalidated automatically The CFIFO still can be invalidated by writing a 1 to the CFINVx bit in Section 24 5 2 7 EQADC CFIFO Control Registers EQADC_CFCR Certify that CFS has changed to IDLE before setting CFINVx The TC_CFx value also is not reset automatically but it can ...

Page 1048: ... single scan software trigger mode Single Scan Edge Trigger When SSS is asserted and an edge triggered mode is selected for a CFIFO an appropriate edge on the associated trigger signal causes the CFIFO to become TRIGGERED For example if rising edge trigger mode is selected the CFIFO becomes TRIGGERED when a rising edge is sensed on the trigger signal The CFIFO commands start to be transferred when...

Page 1049: ...es looping through a sequence of command messages in a CQueue are executed When a CFIFO is programmed for a continuous scan mode the SSE bit in the Section 24 5 2 7 EQADC CFIFO Control Registers EQADC_CFCR does not have any effect Continuous Scan Software Trigger When a CFIFO is programmed to continuous scan software trigger mode the CFIFO is triggered immediately The CFIFO commands start to be tr...

Page 1050: ... asserted and the CFIFO status is changed to WAITING FOR TRIGGER Command transfers will restart as the gate opens If the gate closes and opens during the same serial transmission of a command to the external device it will have no effect on the CFIFO status or on the PF flag but the TORF flag will become asserted as was exemplified in Figure 24 66 on page 1055 Therefore closing the gate for a peri...

Page 1051: ...also stops transfers from the CFIFO when CFIFO status changes from TRIGGERED due to the detection of a closed gate 5 1 Refer to Section 24 6 4 7 2 CQueue Completion Status for more information on EOQ 2 Refer to Section 24 6 4 7 3 Pause Status for more information on Pause 3 EQADC always stops command transfers from a CFIFO when the CFIFO operation mode is disabled 4 EQADC always stops command tran...

Page 1052: ... TRIGGER 0b10 CFIFO Mode is programmed to continuous scan edge or level trigger mode OR CFIFO Mode is programmed to single scan edge or level trigger mode and SSS is asserted OR CFIFO Mode is programmed to single scan software trigger mode 3 TRIGGERED 0b11 CFIFO Mode is programmed to continuous scan software trigger mode 4 WAITING FOR TRIGGER 10 IDLE 0b00 CFIFO Mode is modified to disabled mode 5 ...

Page 1053: ...bit asserted at end of command transfer and CFIFO Mode is not modified to disabled OR CFIFO in single scan level trigger mode and the gate closes while no commands are being transferred from the CFIFO and CFIFO Mode is not modified to disabled OR CFIFO in single scan level trigger mode and EQADC detects a closed gated at end of command transfer and CFIFO Mode is not modified to disabled OR CFIFO M...

Page 1054: ...plete scan of the CQueue was performed If a closed gate is detected while no command transfers are taking place it will have immediate effect on the CFIFO status If a closed gate is detected during the serial transmission of a command to the external device it will have no effect on the CFIFO status until the transmission completes When PIE in Section 24 5 2 7 EQADC CFIFO Control Registers EQADC_C...

Page 1055: ...s its first command to CBuffer the CFIFO is constantly transferring commands and the previous command sequence ended the CFIFO resumes command transfers after being interrupted And a command sequence ends when an asserted EOQ bit is detected on the last transferred command CFIFO is in edge trigger mode and asserted PAUSE bit is detected on the last transferred command the CBuffer to which the next...

Page 1056: ...3 CF5_CB0_CM4 CF5_CB2_CM5 CF5_CB1_CM6 EOQ 1 command sequences Example 3 Example 1 Example 2 CQueue with a two command sequences Assuming that these commands are transferred by a CFIFO configured for edge trigger mode and the command transfers are never interrupted the EQADC would check for non coherency of two command sequences one formed by commands 0 1 2 3 and the other by commands 4 5 6 Assumin...

Page 1057: ...Y fields captured at the end of the first serial transmission Thereafter all BUSY fields captured at the end of consecutive serial transmissions are used to check the fullness of that external CBuffer This is done because the EQADC only updates its external CBuffers status record when it receives a serial message resulting that the record kept by the EQADC is always outdated by at least the length...

Page 1058: ... empty event is detected at the same time the EQADC stops checking for the coherency of a command sequence Once command transfers restart continue the non coherency hardware will behave as if the command sequence started from that point Figure 24 71 depicts how the non coherency hardware will behave when a non coherency event is detected NOTE If MODEx is changed to disabled while a CFIFO is transf...

Page 1059: ...CM2 2 CF5_CB1_CM3 3 CF0_CB1_CM0 0 CF0_CB1_CM1 1 CF0_CB1_CM2 2 CF0_CB1_CM3 3 TNXTPTR CF5_CB1_CM0 0 CF5_CB1_CM1 1 CBuffer1 CFIFO5 CFIFO0 TNXTPTR Sent 0 Sent 1 CF5_CB1_CM2 2 CF5_CB1_CM3 3 Sent 0 CF0_CB1_CM1 1 CF0_CB1_CM2 2 CF0_CB1_CM3 3 TNXTPTR CF5_CB1_CM1 0 CF0_CB1_CM0 1 CBuffer1 CFIFO5 CFIFO0 a CFIFO0 and CFIFO5 both have commands to be sent to CBuffer1 and both are not triggered b CFIFO5 becomes t...

Page 1060: ... SSI b CFIFO0 is triggered and sent two commands to CBuffer2 CFIFO5 cannot send commands to CBuffer3 because the EQADC SSI is busy transferring commands from CFIFO0 Execution of first command of CFIFO5 is completed TNXTPTR Sent 0 Sent 1 CF5_CB3_CM2 2 CF5_CB3_CM3 3 Sent 0 Sent 1 Sent 2 CF0_CB2_CM3 3 TNXTPTR CFIFO5 CFIFO0 CF0_CB2_CM1 0 CF0_CB2_CM2 1 CBuffer2 EMPTY 0 CF5_CB3_CM1 1 CBuffer3 EQADC SSI ...

Page 1061: ... Registers EQADC_RFPR to retrieve data from the RFIFO NOTE The DMAC should be configured to read a single result 16 bit data from the RFIFO pop registers for every asserted DMA request it acknowledges Refer to Section 24 7 2 EQADC DMAC Interface for DMAC configuration guidelines NOTE Reading a word a half word or any bytes from EQADC_RFPRx will pop an entry from RFIFOx and the RFCTRx field will be...

Page 1062: ...ssage arrives and RFIFOx is not full the EQADC copies its contents into the entry pointed by the Receive Next Data Pointer The RFIFO counter RFCTRx in Section 24 5 2 9 EQADC FIFO and Interrupt Status Registers EQADC_FISR is incremented by one and the Receive Next Data Pointer x is also incremented by one or wrapped around to point to the next empty entry in RFIFOx However if the RFIFOx is full the...

Page 1063: ...on has only four entries In this example RFIFOx with 16 entries is shown in sequence after popping or receiving entries Data Entry 2 Data Entry 1 POP Next Data Pointer Receive Next Data Pointer RFIFO Pop Register Data from Read from RFIFO Counter Control Logic DMA Done Interrupt DMA Request SkyBlue Line interface by CPU or DMA external device or from on chip ADCs or from Control Signals All RFIFO ...

Page 1064: ...lidation Next Data Pointer Next Data Pointer Last In Valid Entry Empty Entry Receive Pop RFIFOx Some entries received but none popped Next Data Pointer Next Data Pointer Pop RFIFOx No entries received but some popped Next Data Pointer First In Last In Receive Next Data Pointer Receive RFIFOx Entries received until full and none popped Next Data Pointer RFIFOx No entries received but some popped Po...

Page 1065: ...n chip ADCs have an enable bit ADC0 1_EN in the Section 24 5 3 1 ADC0 1 Control Registers ADC0_CR and ADC1_CR which allows the enabling of the ADCs only when necessary When the enable bit for an ADC is negated the clock input to that ADC is stopped The ADCs are disabled out of reset ADC0 1_EN bits are negated to allow for their safe configuration The ADC must only be configured when its enable bit...

Page 1066: ... clock will be divided as showed in Table 24 14 on page 1008 The ADC clock frequency is calculated as below and it must not exceed 15 MHz This is also the maximum frequency of system clock when the ADC0 1_CLK_SEL is asserted Figure 24 74 depicts how the ADC clocks for ADC0 and ADC1 are generated Figure 24 74 ADC0 1 Clock Generation The ADC conversion speed in K samples per second Ksps is calculate...

Page 1067: ...n Example System Clock Frequency 120 MHz ADC0 1_CLK_PS 0 4 System Clock Divide Factor ADC Clock System Clock 120 MHz Differential Conversion Speed with Default Sampling Time 2 cycles Single Ended Conversion Speed with Default Sampling Time 2 cycles 0b00000 2 N A N A N A 0b00001 4 N A N A N A 0b00010 6 N A N A N A 0b00011 8 15 0 MHz 1 0 Msps 938 Ksps 0b00100 10 12 0 MHz 800 Ksps 750 Ksps 0b00101 12...

Page 1068: ...an be reset by writing 0x0000 to the Section 24 5 3 3 ADC Time Base Counter Registers ADC_TBCR with a write configuration command 24 6 6 4 ADC Pre gain Feature Each ADC can be configured to have a selectable input gain as defined in Section 24 5 3 6 Alternate Configuration 1 8 Control Registers ADC_ACR1 8 This means the input signal is sampled and the result is amplified by factor 2 or 4 before th...

Page 1069: ...enerated by ADCs on the external device are directly sent to RFIFOs unchanged The main component of calibration hardware is a Multiply and Accumulate MAC unit one per on chip ADC that is used to calculate the following transfer function which relates a calibrated result to a raw uncalibrated one CAL_RES GCC RAW_RES OCC 2 where CAL_RES is the calibrated result corresponding the input voltage Vi GCC...

Page 1070: ...direct output from the on chip ADCs but passing through the resolution adjustment block The GCC0 1 operand is a 15 bit fixed point unsigned value stored in the Section 24 5 3 4 ADC0 1 Gain Calibration Constant Registers ADC0_GCCR and ADC1_GCCR The GCC is expressed in the GCC_INT GCC_FRAC binary format The integer part of the GCC GCC_INT GCC 1 contains a single binary digit while its fractional par...

Page 1071: ...conversion results from right aligned format of ADC to the left aligned format depending on the selected resolution of the conversion This operation helps the calibration processing to use the calibration coefficients always with the same format The Result Format and Calibration Sub Block formats the returning data into Result Messages and sends them to the RFIFOs1 The returning data can be data r...

Page 1072: ...channel number of ENTRY0 is sent to the MUX Control Logic some cycles before the sampling phase of the command in ENTRY0 starts In this way sampling for the next command can promptly start after the current conversion finishes because the internal capacitance of the multiplexers will be settled by that time allowing for more accurate sampling This is specially important for applications that requi...

Page 1073: ...SSAGE_TAG1 FMT1 CAL1 EMUX1 TBC_CLK_PS 32 bits MA0 MA1 MA2 ENTRY1 ENTRY0 Configuration ENTRY1 ENTRY0 TSR1 ADDR or and DATA ADDR or and DATA Register Data 0 1 CHANNEL_NUMBER0 Time Stamp1 Registers CBuffer1 CBuffer0 Logic Logic FIFO Control Unit EMUX0 REGISTER FIELD Words in shaded boxes represent configuration register fields ADC1_Result1 ADC0_Result0 LST1 LST0 NOTE x 0 1 2 3 4 5 Result Format MESSA...

Page 1074: ...l signals to both the positive and negative terminals of the ADC The differential conversions can only be initiated on four channels DAN0 Channel Change and Sample Start a Command Execution Sequence for Two Non Overlapped Commands b Command Execution Sequence for Two Overlapped Commands Minimum time necessary to perform a single conversion after channel number is changed Channel Change and Sample ...

Page 1075: ...nput Pins ADC Channel Number in CHANNEL_NUMBER Field Analog Pin Name Other Functions Conversion Type ADC Number Binary Decimal AN0 to AN39 Single ended ADC0 ADC1 0000_0000 to 0010_0111 0 to 39 VRH Single ended ADC0 ADC1 0010_1000 40 VRL Single ended ADC0 ADC1 0010_1001 41 50 x VREF 2 Single ended ADC0 ADC1 0010_1010 42 75 x VREF 2 Single ended ADC0 ADC1 0010_1011 43 25 x VREF 2 Single ended ADC0 A...

Page 1076: ...ded ADC1 1100_0010 194 INA_ADC1_4 LVI12 Single ended ADC1 1100_0011 195 INA_ADC1_5 VDD33 Single ended ADC1 1100_0100 196 INA_ADC1_6 LVI33 Single ended ADC1 1100_0101 197 INA_ADC1_7 LVI50 50 Single ended ADC1 1100_0110 198 INA_ADC1_8 VDDEH1A 50 Single ended ADC1 1100_0111 199 Reserved 1100_1000 to 1111_1111 200 to 255 1 The two on chip ADCs can access the same analog input pins but simultaneous con...

Page 1077: ... to 0111_1111 100 to 127 INA_ADC0 1_1 Temp Sensor Single ended ADC0 ADC1 1000_0000 128 INA_ADC0 1_2 Spare Single ended ADC0 ADC1 1000_0001 129 Reserved 1000_0010 to 1010_0001 130 to 161 Reserved ADC1 1010_0010 to 1010_0111 162 to 167 INA_ADC0_3 VDDEH1B 50 Single ended ADC0 1010_0010 162 INA_ADC0_4 VDDEH4A 50 Single ended ADC0 1010_0011 163 INA_ADC0_5 VDDEH4B 50 Single ended ADC0 1010_0100 164 INA_...

Page 1078: ...tiplexed address signals MA0 MA1 and MA2 to select one of eight inputs These three multiplexed address signals are connected to all four external multiplexer chips The analog output of the four multiplex chips are each connected to four separate EQADC inputs ANW ANX ANY and ANZ The MA pins correspond to the three least significant bits of the channel number that selects ANW ANX ANY and ANZ with MA...

Page 1079: ...essage The EQADC also converts the proper input channel ANW ANX ANY and ANZ by interpreting the CHANNEL_NUMBER field As a result up to 32 externally multiplexed channels appear to the conversion queues as directly connected signals 69 77 85 93 1 0 1 70 78 86 94 1 1 0 71 79 87 95 1 1 1 1 0 means pin is driven LOW and 1 that pin is driven HIGH Table 24 33 Encoding of MA Pins1 continued Channel Numbe...

Page 1080: ...FIFO and Interrupt Status Registers EQADC_FISR Table 24 80 depicts all interrupts and DMA requests generated by the EQADC Table 24 34 EQADC FIFO Interrupt Summary1 Interrupt Condition Clearing Mechanism Non Coherency Interrupt NCIEx 1 NCFx 1 Clear NCFx bit by writing a 1 to the bit MA0 MA1 MA2 MUX AN64 AN65 AN66 AN67 AN68 AN69 AN70 AN71 MUX AN72 AN73 AN74 AN75 AN76 AN77 AN78 AN79 MUX AN80 AN81 AN8...

Page 1081: ...atus Registers EQADC_FISR and Section 24 5 2 8 EQADC Interrupt and DMA Control Registers EQADC_IDCR 2 Apart from generating an independent interrupt request for when a RFIFO Overflow Interrupt a CFIFO Underflow Interrupt and a CFIFO Trigger Overrun Interrupt occurs the EQADC also provides a combined interrupt request at which these requests from ALL CFIFOs are ORed Refer to Figure 24 80 for detail...

Page 1082: ...Fx CFUIEx CFUFx RFOIEx RFOFx Non Coherency Interrupt Request Pause Interrupt Request End of Queue Interrupt Request Trigger Overrun Interrupt Request CFIFO Underflow Interrupt Request RFIFO Overflow Interrupt Request Combined Interrupt Request CFFSx RFDEx RFDFx RFIFO Drain Interrupt Request RFDSx RFDEx RFDFx RFIFO Drain DMA Request RFDSx DMA Request Generation Logic CFFEx CFFFx CFIFO Fill DMA Requ...

Page 1083: ...the end or the abort of a transmission SDI is the master serial data input and SDO the master serial data output The EQADC SSI sub block is enabled by setting the ESSIE field in the Section 24 5 2 1 EQADC Module Configuration Register EQADC_MCR When enabled the EQADC SSI can be optionally capable of starting serial transmissions When serial transmissions are disabled ESSIE set to 0b10 no data will...

Page 1084: ... Data Transmission Protocol Figure 24 83 shows the timing of an EQADC SSI transmission operation The main characteristics of this protocol are FCK is free running it does not stop between data transmissions FCK will be driven low When the serial interface is disabled In stop debug mode Immediately after reset Frame size is fixed to 26 bits MSB bit is always transmitted first Master drives data on ...

Page 1085: ...ed as a clock Although the EQADC SSI behavior is described in terms of the FCK positive and negative edges all EQADC SSI related signals SDI SDS SDO and FCK are synchronized by the system clock on the master side There are no restrictions regarding the use of the FCK as a clock on the slave device 24 6 9 1 1 Abort Feature The master indicates it is aborting the current transfer by negating SDS bef...

Page 1086: ...Protocol Timing 2 3 23 24 25 26 2 3 23 24 25 2 3 23 24 25 2 3 23 24 25 FCK SDS SDO Master Sample SDI Slave Sample Input Input tDT Begin Transmission Begin Transmission End Transmission End Transmission 1 26 26 26 1 1 MSB 1 1 MSB MSB MSB MSB tMDT Minimum tDT is programmable and defined in the Section 24 5 2 13 EQADC SSI Control Register EQADC_SSICR ...

Page 1087: ...of FCK Master s SDI 25 26 1 2 3 25 26 1 2 3 25 26 1 1 2 3 SDS FCK Slave Sample Input tDT tDT tDT Begin Transmission Begin Transmission Begin Transmission End Transmission End Transmission SDS is asserted before positive edge of FCK Slave drives second bit due to detection of an asserted SDS on the negative edge of FCK Slave drives MSB bit again due to detection of a negated SDS on the negative edg...

Page 1088: ...n result data When the DEST field is not zero as described in Section 24 5 3 6 Alternate Configuration 1 8 Control Registers ADC_ACR1 8 the MESSAGE_TAG bits and some control bits and the conversion result data are sent to the transmission section of the PSI sub block This set of data is processed and sent to the corresponding on chip companion module The companion module can also send back to EQAD...

Page 1089: ...trol of the companion module MESSAGE_TAG 0 3 Message tag bits field Read Input Write Output Data Buses Content 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 TAG 0 3 W FLU SH CTRL 0 1 MESSAGE_TAG 0 3 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RESULT_DATA 0 15 W ADC_CONV_RESULT 0 15 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 2...

Page 1090: ...tion The transmission sub block formats the data bus from RFIFO control sub block to send to the PSI Sky Blue wdata bus The transmission data is registered and its content is described in Section 24 6 10 1 Input Output Signals Description The transmission has higher priority than reception This is done to avoid the use of memory to store transmission data and it is not used waiting time for transm...

Page 1091: ...g a bias current I for each ADC associated with the EQADC Through utilizing a 1 resistor R3 the bias current becomes immune to chip process variation Thus the analog circuitry is designed assuming a tighter tolerance on the bias current As a result an analog size and power improvement is gained Refer to the SoC guide for I and R3 values R R VDDA 5V VSSA 0V REFBYPC R3 1 Low Impedance Connection I B...

Page 1092: ...om the RSD stage output back to its input to be passed again To complete a 12 bit conversion the signal must pass through the RSD stage 12 times For 10 bit and 8 bit resolution the signal must pass 10 or 8 times through the RSD Each time an input signal is read into the RSD stage a digital sample is taken by the digital control calculation block The digital control calculation block uses this samp...

Page 1093: ...wo comparator inputs As the Logic Control sets the summing operation it also sends a digital value to the RSD adder Each time an analog signal passes through the RSD single stage a digital value is collected by the RSD adder At the end of an entire AD conversion cycle the RSD adder uses these collected values to calculate the 12 bit 10 bit 8 bit digital output Figure 24 90 shows the transfer funct...

Page 1094: ...e and after each of the 12 passes through the RSD stage Thus 13 total a and b values are collected Upon collecting all these values they will be added according to the RSD algorithm to create the 12 bit digital representation of the original analog input The bits are added in the following manner 24 6 11 2 3 RSD Adder The array s1 to s12 will be the digital output of the RSD ADC with s1 being the ...

Page 1095: ...ions and how such configurations affect the number of effective external signals A complete list of the EQADC external signals can be found in Section 24 4 External Signal Description In the EQADC CFIFO commands have three possible destinations the on chip ADC0 the on chip ADC1 and the external device which is accessible through the EQADC SSI Considering the number of command destinations there ar...

Page 1096: ...ination will still be executed Table 24 38 EQADC External Signal Requirements Pin Name Required for 2ADC_1EXT 1ADC_1EXT Required for 0ADC_1EXT AN0 DAN0 1 1 Used in hard macro factory test Yes No AN1 DAN0 1 AN2 DAN1 1 AN3 DAN1 1 AN4 DAN2 Optional 2 2 Refer to the SoC guide for information on whether these signals are supported or not AN5 DAN2 AN6 DAN3 AN7 DAN3 AN8 ANW 1 Yes AN9 ANX TBIAS 1 AN10 ANY...

Page 1097: ...mmands in CFIFO0 configuration commands could have also been directly written to the CFIFO0 push register 2 Select source driving EQADC hardware trigger ports ETRIG Before proceeding to next step allow some time minimum of two system clocks filter period is set to minimum after reset so that the logic level at the source is filtered and reaches the EQADC control logic NOTE ETRIG ports could be dri...

Page 1098: ...enable the EQADC SSI to start serial transmissions 7 Configure the DMAC to transfer data from CQueue0 to CFIFO0 in the EQADC 8 Configure Section 24 5 2 8 EQADC Interrupt and DMA Control Registers EQADC_IDCR a Set CFFS0 to configure the EQADC to generate a DMA request to load commands from CQueue 0 to the CFIFO0 b Set CFFE0 to enable the EQADC to generate a DMA request to transfer commands from CQu...

Page 1099: ...o configure multiple CQueues to be used for those applications and provides a step by step procedure to configure the EQADC and the associated CQueue structures In the example the Fast hardware triggered CQueue described on the second row of Table 24 39 will have its commands transferred to CBuffer1 the conversion commands will be executed by ADC1 The generated results will be returned to RFIFO3 b...

Page 1100: ...the EQADC Control Registers 3 Configure Section 24 5 2 8 EQADC Interrupt and DMA Control Registers EQADC_IDCR a Set EOQIE1 to enable the End of Queue Interrupt request Table 24 40 Example of CQueue Commands1 1 Fields LST TSR FMT and CHANNEL_NUMBER are not showed for clarity See Section Conversion Command Format for the Standard Configuration for details Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16...

Page 1101: ...en the ones discussed in this section Refer to the block guide of the DMAC used at the SoC level for details 24 7 2 1 CQueue CFIFO Transfers In transfers involving CQueues and CFIFOs the DMAC moves data from a queued source to a single destination as showed in Figure 24 93 The location of the data to be moved is indicated by the source address and the final destination for that data by the destina...

Page 1102: ...ed to by the destination address After the service of a DMA request is completed the destination address has to be updated to point to the location where the next 16 bit result will be stored The source address remains unchanged When the last expected result is written to the RQueue one of the following actions is recommended Refer to the DMAC block guide for details about how this functionality i...

Page 1103: ...t data from RFIF05 d Set RFIFO Drain Enable5 RFDE5 1 in EQADC_IDCR2 2 Configure the Section 24 5 2 7 EQADC CFIFO Control Registers EQADC_CFCR a Write 1 to CFINV5 in EQADC_FCR2 This will invalidate the contents of CFIFO5 b Set MODE5 to Continuous Scan Software Trigger mode in EQADC_CFCR2 3 To transfer a command write it to EQADC CFIFO Push Register 5 EQADC_CFPR5 with Message Tag 0b0101 Refer to Sec...

Page 1104: ... resuming the scan of the queue The TC_CFx provides the point of resumption d Since all result data may not have being stored in the appropriate RFIFO at the time MODEx is changed to disable wait for all expected results to be stored in the RFIFO RQueue before reconfiguring the DMAC to work with the modified RQueue The number of results that must return can be estimated from the TC_CFx value obtai...

Page 1105: ...me only configure them and do not request returning data When a CQueue contains both write and read commands like CQueue0 the CQueue and RQueue entries will not be aligned as shown in Figure 24 95 the result for the second command of CQueue0 is the first entry of RQueue0 The figure also shows that CQueue and RQueue entries can also become unaligned even if all commands in a CQueue request data as ...

Page 1106: ...1 CQueue1 Read Command 1 0x0004 Result to RQueue1 CQueue1 Conversion Command 2 0x0008 Result to RQueue1 CQueue1 Conversion Command m 0x001C Command Queue 1 CQueue1 Result CQueue1 Read Command 0 0x0000 Result Queue 1 RQueue1 Result CQueue1 Read Command 1 0x0002 Result CQueue1 Conversion Command 2 0x0006 Result CQueue0 Conversion Command 3 0x0004 RQueue0 is not aligned with CQueue0 because the first...

Page 1107: ...eference voltages are CAL_RES75 VREF GCC RAW_RES75 VREF OCC 2 CAL_RES25 VREF GCC RAW_RES25 VREF OCC 2 Thus GCC CAL_RES75 VREF CAL_RES25 VREF RAW_RES75 VREF RAW_RES25 VREF OCC CAL_RES75 VREF GCC RAW_RES75 VREF 2 or OCC CAL_RES25 VREF GCC RAW_RES25 VREF 2 After being calculated the GCC and OCC values must be written to ADC registers Section 24 5 3 4 ADC0 1 Gain Calibration Constant Registers ADC0_GC...

Page 1108: ...25 VREF and 75 VREF were respectively 3798 and 11592 The results that should have been obtained from the conversion of these reference voltages are respectively 4096 and 12288 Therefore using equations st plain and st plain the gain and offset calibration constants are GCC 12288 4096 11592 3798 1 05106492 1 05102539 0x4388 OCC 12288 1 05106492 11592 2 102 06 102 0x0066 Table 24 41 shows for this p...

Page 1109: ...arison between the EQADC and QADC in terms of their functionality This section targets the users familiar with terminology in QADC Figure 24 97 is an overview of a QADC Figure 24 98 is an overview of the EQADC system 0 1 2 LSB LSB Input Voltage Digital Value 4 Error for ADC Transfer Curve Shifted Ideal Transfer Curve Transfer Curve 0 Input Voltage 4 2 Quantization Error 2 12 bit AD resolution 12 b...

Page 1110: ...emiconductor Preliminary Subject to Change Without Notice Figure 24 97 QADC Overview External Triggers Result Queues Command Queues Analog to Digital Converter Interrupt Request Digital Control Logic for analog device Trigger and Queue Control Logic ...

Page 1111: ...is implemented to transmit and receive data between the EQADC and the external device Since there are only FIFOs inside the EQADC much of the terminology or use of the register names register contents and signals of the EQADC involve FIFO instead of Queue These register names register contents and signals are functionally equivalent to the Queue counterparts in the QADC Table 24 42 lists how the E...

Page 1112: ...ecting a pause bit in the CCW will pause the queue execution In the EQADC detecting a pause bit in the Command will pause command transfers from a CFIFO Queue Operation Mode MQx CFIFO Operation Mode MODEx The EQADC supports all queue operation modes in the QADC except operation modes related to a periodic timer A timer elsewhere in the system can provide the same functionality if it is connected t...

Page 1113: ...hange Without Notice Queue Execution Require Software or External Trigger events to start queue execution Require Software or External Trigger events to start command transfers from a CFIFO Table 24 43 Usage Comparison between QADC and EQADC System continued Procedure QADC EQADC System ...

Page 1114: ...MPC563XM Reference Manual Rev 1 1114 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 1115: ...e is also provided thus allowing for setting up the filter parameters and the configuration registers The Decimation Filter receives data samples from the master block for example the eQADC in the PSI RX sub block Each sample comes together with an identifier called tag and with some commands The input information is decoded by the PSI RX and Control Logic sub blocks In case of receiving a filteri...

Page 1116: ...tor with 51 bits fixed point Convergent rounding methodology 2 complement overflow or saturation selection Filter takes about 66 clock cycles to filter an input data Implements a local sky blue interface to a master block as the eQADC block Use of parameterized RTL code as much as possible to allow to remove unwanted features Sky Blue interface to SoC Filter taps access for debug Software Reset an...

Page 1117: ... is disabled and it is not possible to enter to the Freeze mode The ipg_clk is stopped And in stop mode the ipg_clk is also stopped 25 2 3 4 Freeze Mode This mode is also known as debug mode 25 2 3 5 Factory Test Mode Refer to Decimation Filter Test Guide 25 3 External Signal Description All signals are internal to the chip and are defined in the integration guide 25 4 Memory Map and Register Defi...

Page 1118: ...cient 0 R W 024 DECFILTER_COEF1 Filter Coefficient 1 R W 028 DECFILTER_COEF2 Filter Coefficient 2 R W 02C DECFILTER_COEF3 Filter Coefficient 3 R W 030 DECFILTER_COEF4 Filter Coefficient 4 R W 034 DECFILTER_COEF5 Filter Coefficient 5 R W 038 DECFILTER_COEF6 Filter Coefficient 6 R W 03C DECFILTER_COEF7 Filter Coefficient 7 R W 040 DECFILTER_COEF8 Filter Coefficient 8 R W 044 077 Reserved 078 DECFILT...

Page 1119: ...s to the Coefficient registers are also allowed The Decimation Filter cannot enter Freeze mode once in disable mode The ipg_enable_clk output goes to disable and ipg_clk is stopped 1 Low Power Mode 0 Normal Mode FREN Freeze Enable The FREN bit enables the Decimation Filter to enter freeze mode if the ipg_debug signal or the FRZ bit is asserted Refer to Section 25 5 12 Freeze Mode Description for m...

Page 1120: ... new input data written to the Interface Input Buffer register or Input Output Buffers register 1 Input Data Interrupt Enabled 0 Input Data Interrupt Disabled ODEN Output Data Interrupt Enable The ODEN bit enables the Decimation Filter to generate interrupt requests on every new data written to the filter Output buffer It is independent of ISEL setting 1 Output Data Interrupt Enabled 0 Output Data...

Page 1121: ...I Sky blue interface can only read the output buffer by request of the decimation filter with the stand alone mode disabled This behavior is presented below in 1 Filter Stand Alone Mode enabled 0 Filter Stand Alone Mode disabled DEC_RATE 3 0 Decimation Rate Selection The DEC_RATE 3 0 field selects the decimation rate used by the Decimation Filter The decimation rate defines the number of data samp...

Page 1122: ...a samples received by the Decimation Filter When the value of this counter matches the DEC_RATE 3 0 Configuration Register field one decimated result is generated and the DEC_COUNTER counter is re initialized at zero IDFC Input Data Flag Clear bit The IDFC bit clears the IDF Flag bit in the Status Register This bit is self negated therefore it is always read as zero 1 Clears IDF 0 No action Table ...

Page 1123: ...atus Register This bit is self negated therefore it is always read as zero 1 Clears IVR 0 No action IDF Input Data Flag The IDF bit flag indicates when a new data is available at the DECFILTER_IB register or at the DECFILTER_IOB register This flag generates an Interrupt Request if enabled by the IDEN bit in the Configuration Register This Flag is cleared by the IDFC Status bit 1 New Sample receive...

Page 1124: ...ation Filter to process a new sample data This operation mode can be used to debug the filter stability or to decimate data in System RAM Once the data is filtered the decimated result is available in the Interface Output Buffer register At this time an interrupt request is issue if enabled Writes to this register when ISEL 0 is forbidden DECFILTER_IB address Decimation Filter base address 010 Fig...

Page 1125: ...ecimation Filter base address 014 Figure 25 5 Interface Output Buffer Register DECFILTER_OB OUTTAG 3 0 Decimation filter output tag bits The OUTTAG 3 0 bit field can be defined as a selector signal and it is used to identify different destinations for the OUTBUF 15 0 data When in stand alone mode ISEL 1 this field is all zero In eQADC application it is used to address the appropriate RFIFO in the ...

Page 1126: ...ILTER_TAPn DECFILTER_TAP address Decimation Filter base address 078 to 094 Figure 25 7 TAPn Register DECFILTER_TAPn TAPn 23 0 Tap n Register The TAPn 23 0 bit fields are the digital filter tap registers The taps are integer signed values in 2 complement format The bit 23 is the sign bit This bit is used to extend the length of tap field When BSY 1 the value of these registers are not specified 0 1...

Page 1127: ...nput data or to bypass a timestamp data It is issued a read request to master block when the decimation filter is not in stand alone mode An interrupt request can also be issued if enabled to indicate to the Core processor that an output data is available DECFILTER_IOB address Decimation Filter address X Figure 25 8 Decimation Filter Interface Input Output Buffers Register DECFILTER_IOB M_FLUSH Ma...

Page 1128: ...dress the appropriate RFIFO in the eQADC block In this case the possible values are only from 0000 to 0101 INP_BUFF 15 0 Input Buffer Data The INP_BUFF 15 0 bit field is the data input from master block The input register can be written by this data when ISEL 0 This data can be a timestamp information that is not processed by the filter or a sample data that is processed by the digital filter In t...

Page 1129: ...l debug capabilities to the Decimation Filter block The MAC Multiply Accumulate sub block executes the filter arithmetic operations controlled by the Control Logic The MAC results are routed to the Filter TAP registers and to the output buffer in the PSI TX side when the result is a decimated filter sample 25 5 2 Parallel Side Interface PSI Description This section describes the operation of the P...

Page 1130: ...g en MAC data load enable set clr new data control logic ips_decfil_rdata ips_decfil_module_en ips_decfil_rwb ipd_decfil_req ips_decfil_wdata decfil_rdata_chain available bypass path timestamp register ips_decfil_rdata ips_decfil_module_en ips_decfil_rwb ipd_decfil_req ips_decfil_wdata decfil_rdata_chain decfilter_2 ips_decfil_rdata ips_decfil_module_en ips_decfil_rwb ipd_decfil_req ips_decfil_wda...

Page 1131: ...uit Figure 25 11 Input buffer Interface Block Diagram 25 5 3 1 Input Buffer Overrun The input overrun occurs when the input buffer is holding an input data and one more data is received by the filter Refer to Section 25 5 3 Input Buffer Description for details of the input buffer The input buffer overrun can occur in the following cases When the input buffer has a sample data to be processed but t...

Page 1132: ...flag ODF is not set When in filter operation mode if the selected source is the local master block ISEL 0 the output buffer receives data from the MAC sub block or from the timestamp storage register The result from the MAC is asked to be written immediately after the processing if the decimation has enabled However the timestamp data is enabled to be written in the output buffer only when the out...

Page 1133: ...dy and the output data flag ODF is not cleared Therefore an output overrun does not occur if the ODF flag is cleared but the output buffer is not read For prefill the output overrun does not occur because the output buffer is not updated For filter operation mode when the filtering result is ready the value is immediately written into the output buffer and the overrun can occur And in bypass mode ...

Page 1134: ... in a direct form This diagram is very close to the filter hardware implementation Note that the number of delay stages is 8 instead of the 4 elements of the Figure 25 13 diagram Figure 25 13 IIR Filter Functional Diagram The difference equation for the IIR filter can be written as Equation 1 where x n is the filter input at time n y n is the filter output at time n N is the number of feed forward...

Page 1135: ...ouble of the IIR filter order since all the TAP and coefficient registers are allocated for the FIR section The Filter configuration paths are shown in Figure 25 15 In this figure multiplexer A controls the bypass filter path and multiplexer B controls selects the filter mode of operation to IIR mode or FIR mode The selection is controlled by the FTYPE 1 0 bits in the Filter Module Configuration r...

Page 1136: ... except when the LS_WORD has the format 1000 00 In this particular case the rounding procedure is like the example of Figure 25 16 If the MS_WORD is odd the value is rounded up Otherwise the word is rounded down There are two locations where the rounding is applied One is to obtain the filter output result with 16 bits and the other is to obtain the IIR feedback result to be stored in tap4 registe...

Page 1137: ...he filter operation to initialize and stabilize the Decimation Filter without generating decimated samples The prefill control comes together with the input data to be filtered When ISEL 0 it is considered the field M_CTRL 1 0 00 in the DECFILTER_IOB register Or the field PREFILL 1 in the DECFILTER_IB register when ISEL 1 The prefill control is usually activated only in a certain number of sample ...

Page 1138: ...the Decimation Filter to execute a partial reset of the filter It is useful for instance when the same filter is used in a new set of data samples after finishing the filtering of another set of data When the flush control is detected all filter TAPs are cleared and the DEC_COUNTER 3 0 field in the status register DECFILTER_MSR is reset The flush function does not clear the Coefficient registers f...

Page 1139: ... is set when the input data sample is processed by the filter and the decimation counter matches the decimation rate value It is defined as an error event in the decimation filter block the overflow in the filter the overrun in the decimation filter input or the overrun in the decimation filter output The overflow occurs when the 2 complement result value from the MAC accumulator is out of the ran...

Page 1140: ...the Decimation Filter receives conversion results generated by the eQADC block These results can be generated from 8 different ADC setup configurations which are identified by an specific eQADC Control address within a Conversion command Conversion commands with Register Address set to zero use the standard configuration setup The samples generated by the standard configuration setup are sent to o...

Page 1141: ... The coefficients were calculate using the Digital Filter Design tool of the SPW software We have supplied some hypothetical filter parameters to the tool and obtained the filter coefficients The input parameters are Filter characteristics Elliptic Low Pass Filter type 4th order IIR Input sample rate 800k sample s Passband edge 100 kHz Stopband edge 150 kHz Passband attenuation 1 dB The software t...

Page 1142: ...ample 1 It is supposed the input data are signed values in the 2 complement format in the range 1 sample 1 Table 25 8 Coefficient values given by SPW digital filter design tool Coefficient Decimal Value Coefficient Decimal Value B0 0 0221455 A0 1 0 B1 0 00445582948893748 A1 2 69772868375858 B2 0 0318517846509088 A2 3 234056294853 B3 0 00445582948893748 A3 1 92028561712454 B4 0 0221455 A4 0 4793908...

Page 1143: ...ter block was used in a Verilog simulator using the calculated coefficients and the input data samples It was used scaling factor 8 in the configuration register DECFILTER_MCR and no decimation factor to obtain the maximum of output results from the filter The theoretical expected values from this filter were also calculated and these results were compared with those from the decimation filter The...

Page 1144: ...MPC563XM Reference Manual Rev 1 1144 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 1145: ... rate up to 50 MHz Figure 26 1 describes the pad signals interface Figure 26 1 LVDS Transmitter Pad Block Diagram Signals lvds_opt0 and lvds_opt1 control the voltage swing on the LVDS pad These two signals are controlled by bits SRC 1 0 of the respective PCR register Table 26 1 gives the configuration for these bits 26 2 Introduction Figure 26 2 is a block diagram of the Deserial Serial Peripheral...

Page 1146: ...des a synchronous serial bus for communication between an MCU and an external peripheral device The DSPI supports pin count reduction through serialization and deserialization of parallel signals transmitted over the SPI serial link The DSPI has three configurations Baud Rate Delay Transfer Control SOUT SIN HT PCS x SS PCSS MTRIG Shift Register SPI SCK SPI and DSI Internal Internal Parallel Inputs...

Page 1147: ...ugh host software Figure 26 3 shows a DSPI with external queues in system RAM Figure 26 3 DSPI with Queues and DMA 26 2 2 Features The DSPI supports these SPI features Full duplex three wire synchronous transfers Master and Slave Mode Buffered transmit operation using the TX FIFO with parameterized depth of 1 to 16 entries Buffered receive operation using the RX FIFO with parameterized depth of 1 ...

Page 1148: ...e DSPI also supports pin reduction through serialization and deserialization Two sources of serialized data DSPI memory mapped register Parallel Input signals Deserialized data is provided as Parallel Output signals and as bits in a memory mapped register Transfer initiation conditions Continuous Edge sensitive hardware trigger Change in data Support for parallel and serial chaining of up to four ...

Page 1149: ... The DSPI has six modes of operation that can be divided into two categories block specific modes such as Master Slave and Module Disable Modes and MCU specific modes like External Stop Factory Test and Debug Modes The block specific modes are entered by host software writing to a register The MCU specific modes are controlled by signals external to the DSPI The MCU specific modes are modes that t...

Page 1150: ...ent and debugging If the SoC enters Debug Mode while the FRZ bit in the DSPI_MCR is set the DSPI stops all serial transfers If the SoC enters Debug Mode while the FRZ bit is negated the DSPI behavior is unaffected and remains dictated by the block specific mode and configuration of the DSPI 26 3 External Signal Description 26 3 1 Overview Table 26 2 lists the signals that may connect off chip depe...

Page 1151: ...when a change in data to be serialized occurs The MTRIG pulse is four system clock cycles in duration If the DSPI is in Slave Mode and the MTO is disabled the PCS 4 MTRIG signal is unused 26 3 2 4 PCS 5 PCSS Peripheral Chip Select 5 Peripheral Chip Select Strobe PCS 5 is a Peripheral Chip Select output signal When the DSPI is in Master Mode and PCSSE bit in the DSPI_MCR is negated this signal is u...

Page 1152: ...tion 26 4 1 Memory Map Register accesses to memory addresses that are reserved or undefined result in a transfer error Write access to the DSPI_POPR register also result in a transfer error Table 26 3 shows the DSPI memory map Table 26 3 DSPI Memory Map Address Register Name DSPI_BASE DSPI Module Configuration Register DSPI_MCR DSPI_BASE 0x4 Reserved DSPI_BASE 0x8 DSPI Transfer Count Register DSPI...

Page 1153: ..._ASDR DSPI_BASE 0xC8 DSPI DSI Transmit Comparison Register DSPI_COMPR DSPI_BASE 0xCC DSPI DSI Deserialization Data Register DSPI_DDR DSPI_BASE 0xD0 DSPI DSI TSB Configuration Register 1 DSPI_DSICR1 1 The number of CTAR registers is parameterized in RTL 2 FIFO Depths are parameterized in RTL Address DSPI_BASE Access 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MSTR CONT_SCKE DCONF FRZ MTFE PCSSE ROOE PC...

Page 1154: ...nabled 6 PCSSE Peripheral Chip Select Strobe Enable The PCSSE bit enables the PCS 5 PCSS to operate as an PCS Strobe output signal See Section 26 5 6 5 Peripheral Chip Select Strobe Enable PCSS for more information 0 PCS 5 PCSS is used as the Peripheral Chip Select 5 signal 1 PCS 5 PCSS is used as an active low PCS Strobe signal 7 ROOE Receive FIFO Overflow Overwrite Enable The ROOE bit enables an...

Page 1155: ... 3 3 FIFO Disable Operation for details 0 RX FIFO is enabled 1 RX FIFO is disabled 20 CLR_TXF Clear TX FIFO CLR_TXF is used to flush the TX FIFO Writing a 1 to CLR_TXF clears the TX FIFO Counter The CLR_TXF bit is always read as zero 0 Do not clear the TX FIFO Counter 1 Clear the TX FIFO Counter 21 CLR_RXF Clear RX FIFO CLR_RXF is used to flush the RX FIFO Writing a 1 to CLR_RXF clears the RX Coun...

Page 1156: ...sters are used to set the slave transfer attributes See the individual bit descriptions for details on which bits are used in Slave Modes When the DSPI is configured as a SPI Master the CTAS field in the command portion of the TX FIFO entry selects which of the DSPI_CTAR register is used When the DSPI is configured as a SPI bus Slave the DSPI_CTAR0 register is used Address DSPI_BASE 0x8 Access 0 1...

Page 1157: ...eld Descriptions 0 DBR Double Baud Rate The DBR bit doubles the effective baud rate of the Serial Communications Clock SCK This field is only used in Master Mode It effectively halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock SCK When the DBR bit is set the duty cycle of the Serial Communications Clock SCK depends on the ...

Page 1158: ...e of SCK and changed on the following edge 1 Data is changed on the leading edge of SCK and captured on the following edge 7 LSBFE LSB First The LSBFE bit selects if the LSB or MSB of the frame is transferred first This bit is only used in Master Mode When operating in TSB configuration this bit should be always 1 0 Data is transferred MSB first 1 Data is transferred LSB first 8 9 PCSSCK 0 1 PCS t...

Page 1159: ...CK 0 3 PCS to SCK Delay Scaler The CSSCK field selects the scaler value for the PCS to SCK delay This field is only used in Master Mode The PCS to SCK Delay is the delay between the assertion of PCS and the first edge of the SCK Table 26 15 list the scaler values The PCS to SCK Delay is a multiple of the system clock period and it is computed according to the following equation Eqn 26 1 See Sectio...

Page 1160: ...the following equation Eqn 26 3 See Section 26 5 6 4 Delay after Transfer tDT for more details 28 31 BR 0 3 Baud Rate Scaler The BR field selects the scaler value for the baud rate This field is only used in Master Mode The prescaled system clock is divided by the Baud Rate Scaler to generate the frequency of the SCK Table 26 18 lists the Baud Rate Scaler values The baud rate is computed according...

Page 1161: ... 0110 128 1110 32768 0111 256 1111 65536 Table 26 16 DSPI After SCK Delay Scaler ASC After SCK Delay Scaler Value ASC After SCK Delay Scaler Value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 Table 26 17 DSPI Delay after Transfer Scaler DT Delay after Transfer Scaler Value DT Delay after Transfer Sc...

Page 1162: ...it has no effect This register may not be writable in MDIS Mode due to the use of power saving mechanisms Refer to the chip specific SoC Guide for details 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 Table 26 18 DSPI Baud Rate Scaler BR Baud Rate Scaler Value BR Baud Rate Scaler Value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 409...

Page 1163: ... Flag The EOQF bit indicates that transmission in progress is the last entry in a queue The EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword and the end of the transfer is reached The EOQF bit remains set until cleared by software When the EOQF bit is set the TXRXS bit is automatically cleared 0 EOQ is not set in the executing command 1 EOQ bit is set in the executing...

Page 1164: ...ent from the DMA controller when the RX FIFO is empty 0 RX FIFO is empty 1 RX FIFO is not empty 15 Reserved should be cleared 16 20 TXCTR TX FIFO Counter The TXCTR field indicates the number of valid entries in the TX FIFO The TXCTR is incremented every time the DSPI _PUSHR is written The TXCTR is decremented every time a SPI command is executed and the SPI data is transferred to the shift registe...

Page 1165: ... to generate an interrupt request 0 EOQF interrupt requests are disabled 1 EOQF interrupt requests are enabled 4 TFUF_RE Transmit FIFO Underflow Request Enable The TFUF_RE bit enables the TFUF flag in the DSPI_SR to generate an interrupt request 0 TFUF interrupt requests are disabled 1 TFUF interrupt requests are enabled 5 Reserved should be cleared 6 TFFF_RE Transmit FIFO Fill Request Enable The ...

Page 1166: ...erate a request The RFDF_DIRS bit selects between generating an interrupt request or a DMA request 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt requests or DMA requests are enabled 15 RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select The RFDF_DIRS bit selects between generating a DMA request or an interrupt request When the RFDF flag bit in the DSPI_SR is set ...

Page 1167: ...y used in SPI Master Mode In SPI Slave Mode DSPI_CTAR0 is used The table below shows how the CTAS values map to the DSPI_CTAR registers The number of DSPI_CTAR registers is implementation specific 4 EOQ End Of Queue The EOQ bit provides a means for host software to signal to the DSPI that the current SPI transfer is the last in a queue At the end of the transfer the EOQF bit in the DSPI_SR is set ...

Page 1168: ... 0x38 Access 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 10 DSPI POP RX FIFO Register DSPI_POPR Table 26 22 DSPI_POPR Field Descriptions Field Description 0 15 Reserved should be cleared 16 31 RXDATA 0 15 Received Data The RX...

Page 1169: ...st not write to the DSPI_DSICR while the DSPI is in the Running state Table 26 23 DSPI_TXFRn Field Descriptions Field Description 0 15 TXCMD 0 15 Transmit Command The TXCMD field contains the command that sets the transfer attributes for the SPI data See Section 26 4 2 6 DSPI PUSH TX FIFO Register DSPI_PUSHR for details on the command field 16 31 TXDATA 0 15 Transmit Data The TXDATA field contains...

Page 1170: ...be one more than the value in the MTOCNT field The number of SCK cycles defined by MTOCNT must be equal to or greater than the frame size When TSBC is set MTOCNT is not used and its value is ignored 8 10 Reserved should be cleared 11 TSBC Timed Serial Bus Configuration The TSBC bit enables the Timed Serial Bus Configuration This configuration allows 32 bit data to be used It also allows tDT to be ...

Page 1171: ... is used for both DSICR and DSICR1 registers 16 DCONT DSI Continuous Peripheral Chip Select Enable The DCONT bit enables the PCS signals to remain asserted between transfers The DCONT bit only affects the PCS signals in DSI Master Mode See Section 26 5 7 5 Continuous Selection Format for details When TSBC bit is set DCONT bit is used for both DSICR and DSICR1 registers 0 Return Peripheral Chip Sel...

Page 1172: ...re only used when TSB is enabled For non TSB configurations only the least 16 significant bits are used Address DSPI_BASE 0xC0 Access 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SER_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SER_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 26 14 DSPI DSI Serialization Data Register DSPI_SDR Table 26 27 DSPI_SD...

Page 1173: ...R register holds the signal states for the Parallel Output signals The DSPI_DDR is read only and it is memory mapped so that host software can read the incoming DSI frames Table 26 28 DSPI_ASDR Field Descriptions Field Descriptions 0 31 ASER_DATA 0 31 Alternate Serialized Data The ASER_DATA field holds the alternate data to be serialized Address DSPI_BASE 0xC8 Access 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 1174: ...ta Register DSPI_DDR Table 26 30 DSPI_DDR Field Descriptions Field Descriptions 0 15 DESER_DAT A 0 15 Deserialized Data When TSB configuration is set the DESER_DATA field holds deserialized data which is presented as signal states to the Parallel Output signals If TSB is disabled these bits are ignored and only the lower 16 bits are valid 16 31 DESER_DAT A 0 15 Deserialized Data The DESER_DATA fie...

Page 1175: ...use See Section 26 4 2 3 DSPI Clock and Transfer Attributes Registers 0 7 DSPI_CTAR0 DSPI_CTAR7 for information on the fields of the DSPI_CTAR registers The 16 bit shift register in the Master and the 16 bit shift register in the Slave are linked by the SOUT and SIN signals to form a distributed 32 bit register The Master and Slave use 16 bit shift registers regardless the TSBC bit is asserted in ...

Page 1176: ...g Features for information on the power saving features of the DSPI 26 5 1 Modes of Operation The DSPI has six distinct modes Master Mode Slave Mode Module Disable Mode External Stop Mode Factory Test Mode Debug Mode Master Slave and Module Disable Modes are block specific mode while External Stop Factory Test and Debug Modes are MCU specific modes The block specific modes are determined by bits i...

Page 1177: ...d by a bus master by having the slave s SS asserted In Slave Mode the SCK is provided by the bus master All transfer attributes are controlled by the bus master but clock polarity clock phase and numbers of bits to transfer must still be configured in the DSPI slave for proper communications The SPI and DSI configurations are valid in Slave Mode In SPI Slave Mode the slave transfer attributes are ...

Page 1178: ...d by an external controller See Figure 26 20 for a state diagram 26 5 2 Start and Stop of DSPI Transfers The DSPI has two operating states STOPPED and RUNNING The states are independent of DSPI configuration The default state of the DSPI is STOPPED In the STOPPED state no serial transfers are initiated in Master Mode and no transfers are responded to in Slave Mode The STOPPED state is also a safe ...

Page 1179: ... is that in Master Mode the DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO entry In Slave mode the DSPI only responds to transfers initiated by a bus master external to the DSPI and the SPI command field of the TX FIFO entry is ignored 26 5 3 1 Master Mode In SPI Master Mode the DSPI initiates the serial transfers by controlling the Serial ...

Page 1180: ...ering Mechanism The TX FIFO functions as a buffer of SPI data and SPI commands for transmission The TX FIFO holds from one to sixteen words each consisting of a command field and a data field The number of entries in the TX FIFO is SoC specific SPI commands and data are added to the TX FIFO by writing to the DSPI PUSH TX FIFO Register DSPI_PUSHR TX FIFO entries can only be removed from the TX FIFO...

Page 1181: ... into the RX FIFO SPI data are removed popped from the RX FIFO by reading the DSPI POP RX FIFO Register DSPI_POPR RX FIFO entries can only be removed from the RX FIFO by reading the DSPI_POPR or by flushing the RX FIFO The RX FIFO Counter field RXCTR in the DSPI Status Register DSPI_SR indicates the number of valid entries in the RX FIFO The RXCTR is updated every time the DSPI _POPR is read or SP...

Page 1182: ...MCR is 0b01 The DSI frames can be from four to sixteen bits long but four to 32 bits can be used in the TSB configuration see Section 26 5 9 Timed Serial Bus TSB for detailed information With Multiple Transfer Operation MTO the DSPI supports serial chaining of DSPI blocks within an SoC to create DSI frames consisting of concatenated bits from multiple DSPIs The DSPI also supports parallel chaining...

Page 1183: ...mpled at every rising edge of the system clock The DSPI_ASDR register is written by host software and used as an alternate source of serialized data A copy of the last 32 bit DSI frame shifted out of the Shift Register is stored in the DSPI DSI Transmit Comparison Register DSPI_COMPR This register provides added visibility for debugging and it serves as a reference for transfer initiation control ...

Page 1184: ... has completed and the Delay after Transfer tDT has elapsed 26 5 4 5 2 Change In Data Control For Change in Data Control a transfer is initiated when the data to be serialized has changed since the transfer of the last DSI frame A copy of the previously transferred DSI data is stored in the DSPI_COMPR When the data in the DSPI_SDR or the DSPI_ASDR is different from the data in the DSPI_COMPR a new...

Page 1185: ... SoC to share SCK and PCS signals thereby saving pins The serial chaining allows bits from multiple DSPIs to be concatenated into a single DSI frame MTO is enabled by setting the MTOE bit in the DSPI_DSICR In parallel and serial chaining there is one bus master and multiple bus slaves The bus master initiates and controls the transfers but the DSPI slaves generate trigger signals for the bus DSPI ...

Page 1186: ... signal thereby propagating trigger signals from other DSPI slaves to the DSPI master The MTOCNT field in the DSPI_DSICR must be written with the number of bits to be transferred In parallel chaining the number written to MTOCNT must match the FMSZ field in the selected DSPI_CTAR register 26 5 4 6 2 Serial Chaining The serial chaining allows transfers of DSI frames of up to a total of 64 bits usin...

Page 1187: ... slaves For example if one 16 bit DSI frame is created by concatenating eight bits from the DSPI master and four bits from each of the DSPI slaves in Figure 26 24 the DSPI master s frame size must be set to eight in the FMSZ field and the DSPI slaves frame size must be set to four The largest DSI frame supported by the MTOCNT field is 64 bits Any number of DSPIs can be connected together to concat...

Page 1188: ...the figure as PCSx and PCSy The CSI Configuration is only supported in Master Mode Data returned from the external slave while a DSI frame is transferred is placed on the Parallel Output signals Data returned from the external slave while a SPI frame is transferred is moved to the RX FIFO The TX FIFO and RX FIFO are fully functional in CSI mode 26 5 5 1 CSI Serialization Serialization in the CSI c...

Page 1189: ...ts the appropriate CS signal 26 5 5 2 CSI Deserialization The deserialized frames in CSI Configuration goes into the DSPI_SDR or the RX FIFO based on the transfer priority logic When DSI frames are transferred the returned frames are deserialized and latched into the DSPI_DDR When SPI frames are transferred the returned frames are deserialized and written to the RX FIFO Figure 26 27 shows the CSI ...

Page 1190: ...K Delay tCSC The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge See Figure 26 30 for an illustration of the PCS to SCK delay The PCSSCK and CSSCK fields in the DSPI_CTARx registers select the PCS to SCK delay by the formula in the CSSCK 0 3 bit description Table 26 35 shows an example of how to compute the PCS to SCK delay 26 5 6 3 After SCK Delay tAS...

Page 1191: ...s configurable as outlined in the DSPI_CTARx registers When in continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period When in TSB and continuous mode the delay is programmed as outlined in the DSPI_CTARx registers but in the event that the delay does not coincide with an SCK period in duration the delay is extended to the next SCK active edge Table 26 38 shows an example o...

Page 1192: ...ch free PCS signals Figure 26 29 shows the timing of the PCSS signal relative to PCS signals Table 26 38 Delay after Transfer Computation Example in TSB Configuration PDT field tDT 1 Tsck 1 Some values are not reachable i e 9 11 13 15 17 18 19 to calculate these values please see the Equation 26 3 0 1 2 3 DT field 02 2 The values in this row were rounded to the next integer value 1 2 3 4 1 1 3 5 7...

Page 1193: ...the PCS signals The SCK signal provided by the Master device synchronizes shifting and sampling of the data on the SIN and SOUT pins The PCS signals serve as enable signals for the slave devices When the DSPI is the bus master the CPOL and CPHA bits in the DSPI Clock and Transfer Attributes Registers DSPI_CTARx select the polarity and phase of the serial clock SCK The polarity bit selects the idle...

Page 1194: ...The MTFE bit in the DSPI_MCR selects between Classic SPI Format and Modified Transfer Format The Classic SPI Formats are described in Section 26 5 7 1 Classic SPI Transfer Format CPHA 0 and Section 26 5 7 2 Classic SPI Transfer Format CPHA 1 The Modified Transfer Formats are described in Section 26 5 7 3 Modified SPI DSI Transfer Format MTFE 1 CPHA 0 and Section 26 5 7 4 Modified SPI DSI Transfer ...

Page 1195: ...e data on their SOUT pins on the even numbered clock edges After the last clock edge occurs a delay of tASC is inserted before the master negates the PCS signals A delay of tDT is inserted before a new frame transfer can be initiated by the master 26 5 7 2 Classic SPI Transfer Format CPHA 1 This transfer format shown in Figure 26 31 is used to communicate with peripheral SPI slave devices that req...

Page 1196: ... transfer can be initiated by the master 26 5 7 3 Modified SPI DSI Transfer Format MTFE 1 CPHA 0 In this Modified Transfer Format both the Master and the Slave sample later in the SCK period than in Classic SPI mode to allow for delays in device pads and board traces These delays become a more significant fraction of the SCK period as the SCK period decreases with increasing baud rates The Master ...

Page 1197: ...7 4 Modified SPI DSI Transfer Format MTFE 1 CPHA 1 Figure 26 33 shows the Modified Transfer Format for CPHA 1 Only the condition where CPOL 0 is described At the start of a transfer the DSPI asserts the PCS signal to the slave device After the PCS to SCK delay has elapsed the master and the slave put data on their SOUT pins at the first edge of SCK The Slave samples the Master SOUT signal on the e...

Page 1198: ...figuration by setting the CONT bit in the SPI command Continuous Selection is enabled for the DSI Configuration by setting the DCONT bit in the DSPI_DSICR The behavior of the PCS signals in the two configurations is identical so only SPI Configuration will be described When the CONT bit 0 the DSPI drives the asserted Chip Select signals to their idle states in between frames The idle states of the...

Page 1199: ...PHA 1 and CONT 1 Figure 26 35 Example of Continuous Transfer CPHA 1 CONT 1 Switching CTAR registers or changing which PCS signals are asserted between frames while using Continuous Selection can cause errors in the transfer The PCS signal should be negated before CTAR is switched or different PCS signals are selected tCSC tDT tCSC SCK PCSx SCK Master SOUT Master SIN tCSC PCS to SCK delay tDT Delay...

Page 1200: ...e DSICTAS field shall be used initially At the start of a SPI frame transfer the CTAR specified by the CTAS value for the frame shall be used At the start of a DSI frame transfer the CTAR specified by the DSICTAS field shall be used In all configurations the currently selected CTAR shall remain in use until the start of a frame with a different CTAR specified or the Continuous SCK mode is terminat...

Page 1201: ...K Timing Diagram CONT 1 26 5 9 Timed Serial Bus TSB The DSPI can be programmed in Timed Serial Bus configuration by asserting the TSBC bit in the DSPI_DSICR register see Section 26 4 2 10 DSPI DSI Configuration Register DSPI_DSICR for details To work in TSB configuration the DSPI must be in master mode and configured as DSI DCONF 0b01 The TSB allows operating in Continuous and Non Continuous Seria...

Page 1202: ...ister select the delay after transfer Some values will not be possible see the reference manual for details Figure 26 39 TSB Downstream Frame The Figure 26 39 shows the two types of downstream frames command frame and data frame used in the TSB configuration refer to Section 26 5 9 1 PCS Switch Over Timing and Section 26 5 9 3 TSB Data Frame Format for detailed information The Command Word can be ...

Page 1203: ...me as seen by the slave The exact timing between the external signals SCK and PCS signals will not be exactly aligned due to routing and pad differences This approach ensures that larger shorter SCK periods will result in approximately symmetric increases decreases of setup and hold margins on the PCS signals The setup time for the PCS signals before the first bit of the first part of the frame an...

Page 1204: ...ame can be composed by data bits only or by data bits preceded by a selection bit see Figure 26 41 A data frame with a selection bit always starts with a low level bit at SOUT The number of data bits in the active phase is from 4 to 32 bits and the least significant bit of a data portion is transmitted first LSBFE 1 Figure 26 41 TSB Data Frame Format 26 5 10 Interrupts DMA Requests The DSPI has fo...

Page 1205: ...st is generated 26 5 10 3 Transfer Complete Interrupt Request The Transfer Complete Request indicates the end of the transfer of a serial frame The Transfer Complete Request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPI_RSER 26 5 10 4 Transmit FIFO Underflow Interrupt Request The Transmit FIFO Underflow Request indicates that an underflow condition in the TX...

Page 1206: ...o the shift register If the ROOE bit is negated the incoming data is ignored 26 5 11 Power Saving Features The DSPI supports three power saving strategies External Stop Mode IPI Green Line Stop Mode Module Disable Mode Clock gating of non memory mapped logic Clock gating of IPI SkyBlue signals and clock to memory mapped logic The External Stop Mode requires a block external to the DSPI to implemen...

Page 1207: ...t the memory mapped registers are still accessible Certain read or write operations have a different affect when the DSPI is in the Module Disable Mode Reading the RX FIFO Pop Register will not change the state of the RX FIFO Likewise writing to the TX FIFO Push Register will not change the state of the TX FIFO Clearing either of the FIFOs will not have any affect in the Module Disable Mode Change...

Page 1208: ...he RXCNT in DSPI_SR or by checking RFDF in the DSPI_SR after each read operation of the DSPI_POPR 7 Modify DMA descriptor of TX and RX channels for new queues 8 Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPI_MCR Flush RX FIFO by writing a 1 to the CLR_RXF bit in the DSPI_MCR 9 Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new queue or v...

Page 1209: ...cy This table does not apply for TSB Continuous Mode Table 26 42 Baud Rate Values Baud Rate Divider Prescaler Values 2 3 5 7 Baud Rate Scaler Values 2 25 0M 16 7M 10 0M 7 14M 4 12 5M 8 33M 5 00M 3 57M 6 8 33M 5 56M 3 33M 2 38M 8 6 25M 4 17M 2 50M 1 79M 16 3 12M 2 08M 1 25M 893k 32 1 56M 1 04M 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78 1k 55 8k 512 97 7k 65 1k 39 1k 2...

Page 1210: ...stration but the concepts carry over to the RX FIFO See Section 26 5 3 4 Transmit First In First Out TX FIFO Buffering Mechanism and Section 26 5 3 5 Receive First In First Out RX FIFO Buffering Mechanism for details on the FIFO operation Table 26 43 Delay Values Delay Prescaler Values 1 3 5 7 Delay Scaler Values 2 20 0 ns 60 0 ns 100 0 ns 140 0 ns 4 40 0 ns 120 0 ns 200 0 ns 280 0 ns 8 80 0 ns 24...

Page 1211: ...Depth Transmit FIFO depth implementation specific 26 6 4 2 Address Calculation for the First in Entry and Last in Entry in the RX FIFO The memory address of the first in entry in the RX FIFO is computed by the following equation Eqn 26 9 The memory address of the last in entry in the RX FIFO is computed by the following equation Eqn 26 10 Entry A first in Entry B Entry C Entry D last in Push TX FI...

Page 1212: ...al Rev 1 1212 Freescale Semiconductor Preliminary Subject to Change Without Notice RX FIFO Base Base address of RX FIFO RXCTR RX FIFO counter POPNXTPTR Pop Next Pointer RX FIFO Depth Receive FIFO depth implementation specific ...

Page 1213: ...te Machine The control logic of the LIN hardware MCLK Module Clock defined in Section 27 4 3 1 Module Clock TCLK Transmitter Clock defined in Section 27 4 3 2 Transmitter Clock RCLK Receiver Clock defined in Section 27 4 3 3 Receiver Clock RSC Receiver Sample Counter defined in Section 27 4 3 3 Receiver Clock Table 27 2 Glossary Term Definition Logic level one The voltage that corresponds to Boole...

Page 1214: ...itted byte field or character equivalent to the duration of one transmitter clock cycle defined in Section 27 4 3 2 Transmitter Clock frame Entity that consists of the start bit followed by payload bits followed by one ore more stop bits LIN byte field Special instance of a frame SCI frame Special instance of a frame LIN frame Sequence of LIN byte fields Table 27 2 Glossary continued Term Definiti...

Page 1215: ...rity error Receiver framing error detection 1 16 bit time noise detection 2 channel DMA interface LIN support LIN Master Node functionality master and slave task Compatible with LIN slaves from revisions 1 x and 2 0 of the LIN standard Detection of Bit Errors Physical Bus Errors and Checksum Errors All status bit can generate maskable interrupts Application layer CRC support Programmable CRC polyn...

Page 1216: ...s 27 2 1 1 eSCI Transmit Pin TXD This pin serves as transmit data output and as the receive data input of eSCI 27 2 1 2 eSCI Receive Pin RXD This pin serves as receive data input of the eSCI 27 3 Memory Map and Register Definition This section provides the memory map and a detailed description of the memory mapped registers 27 3 1 Memory Map Table 27 3 Block Memory Map Offset Register Access Gener...

Page 1217: ...ed Read 0x18 LIN CRC Polynomial Register 1 LINCRCP1 Read Write 0x19 LIN CRC Polynomial Register 2 LINCRCP2 Read Write General Registers cont 0x1A SCI Control Register 5 SCICR5 Read Write 0x1B 0x1F Reserved Read Table 27 4 Register Conventions Convention Description Depending on its placement in the read or write row indicates that the bit is not readable or not writeable FIELDNAME Identifies the f...

Page 1218: ... High SCIBDH This register provides the upper part of the baud rate control value SBR The baud rate and clock generation is specified in Section 27 4 3 Baud Rate and Clock Generation 0 Resets to zero 1 Resets to one Address Offset 0x00 Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0 0 Figure 27 2 SCI Baud Rate Register High SCIBDH Table 27 5 SCIBDH Field Des...

Page 1219: ...ontrol value SBR Address Offset 0x02 Access User read write 7 6 5 4 3 2 1 0 R LOOPS R RSRC M WAKE ILT PE PT W Reset 0 0 0 0 0 0 0 0 Figure 27 4 SCI Control Register 1 SCICR1 Table 27 7 SCICR1 Field Descriptions Field Description 7 LOOPS Loop Mode Select This control bit together with the RSRC control bit defines the receiver source mode The mode coding is defined in Table 27 8 and the modes are de...

Page 1220: ...ts after reception of a low bit 1 Idle line detection starts after reception of the last stop bit 1 PE Parity Enable This control bit enables the parity bit generation and checking The location of the parity bits is shown in Section 27 4 2 Frame Formats 0 Parity bit generation and checking disabled 1 Parity bit generation and checking enabled 0 PT Parity Type This control bit defines whether even ...

Page 1221: ...interrupt request generation enabled 3 TE Transmitter Enable This control bit enables and disables the transmitter The control features of the transmitter are described in Section 27 4 5 2 1 Transmitter States and Transitions 0 Transmitter disabled 1 Transmitter enabled 2 RE Receiver Enable This control bit enables and disables the receiver The control features of the receiver are described in Sec...

Page 1222: ...egister 2 SCISR2 and physical bus errors are indicated by the PBERR flag in the LIN Status Register 1 LINSTAT1 0 Transmit DMA requests generated regardless of bit errors or physical bus errors 1 Transmit DMA requests are not generated if SCISR2 BERR flag or LINSTAT1 PBERR flag are set Note This bit is used in LIN mode only 4 BERRIE Bit Error Interrupt Enable This bit controls the BERR interrupt re...

Page 1223: ...n polarity This bit controls the polarity of the RXD pin See Section 27 4 2 1 1 Inverted Data Frame Formats 0 Normal Polarity 1 Inverted Polarity 4 PMSK Parity Bit Masking This bit defines whether the received parity bit is presented in the related bit position in the SCI Data Register High SCIDRH or SCI Data Register Low SCIDRL 0 The received parity bit is presented in the bit position related to...

Page 1224: ...eived data bit 8 or address bit M2 0 M 1 PE 1 value of received parity bit if SCICR4 PMSK 0 0 otherwise M2 1 M 0 PE 1 value of received parity bit if SCICR4 PMSK 0 0 otherwise M2 1 M 1 PE 1 value of received parity bit if SCICR4 PMSK 0 0 otherwise It is 0 for all other frame formats 6 TN Transmit Most Significant Bit The semantic of this bit depends on the frame format selected by SCICR5 M2 SCICR1...

Page 1225: ...ransmit bits 6 to 0 Value of bit Tx is transmitted in BITx Address Offset 0x08 Access User read write to clear 7 6 5 4 3 2 1 0 R TDRE TC RDRF IDLE OR NF FE PF W w1c w1c w1c w1c w1c w1c w1c w1c Reset 1 0 0 0 0 0 0 0 Figure 27 10 SCI Status Register 1 SCISR1 Table 27 14 SCISR1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag This flag is set when the content of the SCI D...

Page 1226: ...aming error during the reception of that frame as described in Section 27 4 5 3 18 Stop Bit Verification 0 PF Parity Error Flag This flag is set when the payload data of a received frame was transferred into the SCI Data Register High SCIDRH and SCI Data Register Low SCIDRL and the receiver has detected a parity error for the character as described in Section 27 4 5 4 Reception Error Reporting Not...

Page 1227: ... when the content of the LIN TX Register LINTX was transferred into internal transmit shift register 5 LWAKE LIN Wakeup Received Flag This flag is set when a LIN Wakeup character was received as described in Section 27 4 6 6 LIN Wakeup 4 STO Slave Timeout Flag This flag is set when a slave does not complete a frame within the specified maximum frame length which is defined in Section 27 4 6 5 LIN ...

Page 1228: ... write with no ongoing transmissions 7 6 5 4 3 2 1 0 R LRES 0 WUD LDBG DSF PRTY LIN W WU Reset 0 0 0 0 0 0 0 0 Figure 27 14 LIN Control Register 1 LINCTRL1 Table 27 18 LINCTRL1 Field Descriptions Field Description 7 LRES LIN FSM Resync This bit controls the state of the LIN protocol engine 0 LIN protocol engine in normal mode 1 LIN protocol engine hold in initial state 6 WU LIN Bus Wake Up Trigger...

Page 1229: ...nable This bit controls the LINSTAT1 RXRDY interrupt request generation 0 RXRDY interrupt request generation disabled 1 RXRDY interrupt request generation enabled 6 TXIE Transmit Data Ready Interrupt Enable This bit controls the LINSTAT1 TXRDY interrupt request generation 0 TXRDY interrupt request generation disabled 1 TXRDY interrupt request generation enabled 5 WUIE LIN Wakeup Received Interrupt...

Page 1230: ...ddress Offset 0x0E Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 UQIE OFIE W Reset 0 0 0 0 0 0 0 0 Figure 27 16 LIN Control Register 3 LINCTRL3 Table 27 20 LINCTRL3 Field Descriptions Field Description 1 UQIE Unrequested Data Received Interrupt Enable This bit controls the LINSTAT2 UREQ interrupt request generation 0 UREQ interrupt request generation disabled 1 UREQ interrupt request generation enab...

Page 1231: ...rame Table 27 21 LINTX Field Descriptions Field Description P 1 0 Identifier Parity This field provides the identifier parity which is used to create the protected identifier if the automatic identifier parity generation is disabled i e the PRTY bit in LIN Control Register 1 LINCTRL1 is 0 ID 5 0 Identifier This field is used for the identifier field in the protected identifier LEN Frame Length Thi...

Page 1232: ...scribed in Section 27 4 6 5 5 Slave Timeout Detection TX frame Must be set to 0 DATA Transmit Data Data bits for transmission Address Offset 0x14 Access User read 7 6 5 4 3 2 1 0 R D 7 0 W Reset 0 0 0 0 0 0 0 0 Figure 27 19 LIN RX Register LINRX Table 27 22 LINRX Field Descriptions Field Description 7 0 D 7 0 Receive Data This field provides the data bytes of received LIN RX frames Address Offset ...

Page 1233: ...ptions Field Description 4 SYNM Synchronization Mode This bit controls the synchronization mode of the receiver The synchronization modes are described in Section 27 4 5 3 14 Bit Synchronization 0 Synchronization performed at falling start and data bit edge 1 Synchronization performed at falling start bit edge only 3 EROE ERR flag overrun enable 0 SCIDRH ERR flag not affected by overrun detection ...

Page 1234: ...idle characters 27 4 2 1 Data Frame Formats Each data frame contains a character that is surrounded by a start bit an optional parity or address bit and one or two stop bits The supported data frame formats for transmission and reception are specified in Table 27 25 The supported data frame formats for reception only are specified in Table 27 26 Table 27 25 Supported Data Frame Formats for RX and ...

Page 1235: ...s 2 stop bits Table 27 26 Supported Data Frame Formats for RX only Control Frame Content SCICR5 SCICR1 Start Bits Payload Bits Stop Bits M2 M PE WAKE Character Bits Address Bits Parity Bits SCI Frames 2 stop bits see Figure 27 26 1 0 1 0 1 8 0 1 2 1 1 1 0 1 12 0 1 2 BIT0 START BIT STOP BIT BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT0 START BIT STOP BIT BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT0 START BIT ADDR ...

Page 1236: ... and content of the LIN break symbols is shown in Figure 27 28 Figure 27 28 LIN Break Symbol Format The structure and content of the SCI break characters is shown in Figure 27 29 Table 27 27 Supported Break Character Formats Control1 1 All codings which are not listed are reserved and must not be used Break Character Content SCICR5 SCICR1 SCICR3 Start Bit Character Bits Delemit Bits M2 M BRCL LIN ...

Page 1237: ... value written to the SBR field in the SCI Baud Rate Register High SCIBDH and SCI Baud Rate Register Low SCIBDL determines the module clock divisor The baud rate clock is Table 27 28 Supported Idle Character Formats Control Idle Character Length SCICR5 SCICR1 M2 M SCI Idle Characters see Figure 27 30 0 0 10 0 1 11 1 0 12 1 1 16 BIT0 START BIT BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT0 START BIT ...

Page 1238: ...k TCLK is used to drive the data to the serial bus via the TXD pin It is derived from the system bus clock by the baud rate generator The baud rate generator is controlled by the value of the SBR 12 0 field in the SCI Baud Rate Register High SCIBDH and SCI Baud Rate Register Low SCIBDL The frequency of the transmitter clock is determined by Equation 27 1 and defines the length of the transmitted b...

Page 1239: ...ogical value 1 A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RS8 RS9 and RS10 stop bit samples are a logic zero 27 4 4 1 Faster Receiver Tolerance In this case the receiver has a higher baud rate than the transmitter thus the stop bit sampling starts already in the last transmitted payload bit To ensure the correct noise and framing error fre...

Page 1240: ...ted in the transmitted stop bit as shown in Figure 27 32 Figure 27 32 Slower Receiver The maximum tolerance that ensures error free reception can be calculated with the assumption that RS11 is sampled in the transmitted start bit and RS10 is sampled in the last stop bit For an frame with n payload bits and s stop bits the transmitter starts the transmission of the next start bit Eqn 27 7 after the...

Page 1241: ...INCTRL1 LIN 0 select baud rate SCI Baud Rate Register High SCIBDH and SCI Baud Rate Register Low SCIBDL select receiver input mode SCI Control Register 1 SCICR1 LOOPS SCI Control Register 1 SCICR1 RSRC select frame format SCI Control Register 1 SCICR1 M SCI Control Register 1 SCICR1 PE SCI Control Register 1 SCICR1 WAKE SCI Control Register 5 SCICR5 M2 select parity type SCI Control Register 1 SCI...

Page 1242: ...he state of the transmitter is changed as shown in Figure 27 33 and the action given in Table 27 33 is executed The module transition shown in Table 27 34 are triggered when the described condition or event occurs The send break bit SBK in the SCI Control Register 2 SCICR2 is check for the start condition The internal commit bit iCMT the transmitter active bit TACT in the SCI Status Register 2 SCI...

Page 1243: ... bit if configured and the configured number of stop bits When the last stop bit has been transmitted and the application has not disabled the transmitter the transmitter returns to the Ready state via the done transition If no frame or character transmit request is pending the transfer complete flag TC in the SCI Status Register 1 SCISR1 is set If the application has disabled the transmitter whil...

Page 1244: ... entering this mode the application should perform the following actions 1 Configure the module for SCI mode 2 Enable the transmitter by setting TE in SCI Control Register 2 SCICR2 to 1 3 Setup the DMA controller channel and provide frame data in system memory A block diagram which presents an overview of the DMA Controlled Date Frame Transmission is shown in Figure 27 34 Figure 27 34 DMA Controll...

Page 1245: ...nsmitter the transmitter continues to transmit the current break character and after it has finished the transmission of this break character it transmits a stop bit The stop bit at the end of a break character sequence guarantees the recognition of the start bit of the next data frame After the transmission of the stop bit and if the application has not disabled the transmitter the transmitter re...

Page 1246: ...s changed as shown in Figure 27 35 and the action given in Table 27 37 is executed The module transition shown in Table 27 38 are triggered when the described event occurs Table 27 36 Receiver States State Indication Description RE RACT RWU Idle 0 0 0 Receiver is disabled and no reception is running Ready 1 0 0 Receiver is enabled and no reception is running Run 1 1 0 Receiver is enabled and recep...

Page 1247: ...Mode 27 4 5 3 4 Single Wire Mode In Single Wire Mode the RXD pin is disconnected from the eSCI module and the TXD pin is used for both receiving and transmitting Figure 27 37 Single Wire Mode Table 27 38 Receiver Module Transition Transition Condition Action Description start State Ready Run and start bit received RACT 1 Start of reception of data frame or break character done State Run and idle c...

Page 1248: ...racters are processed as data frames Due to the received 0 at the stop bit location the reception of a break character causes at least a framing error The error reporting is performed as described in Section 27 4 5 4 Reception Error Reporting 27 4 5 3 8 Idle Character Detection The start point of the idle character detection is controlled by the idle line type bit ILT in the SCI Control Register 1...

Page 1249: ...zes the connected DMA channels A block diagram which presents an overview of the DMA Controlled SCI Data Frame reception is shown in Figure 27 39 The RX DMA channel is used to transfer the received frame data into the memory When new data was received the module generates the receive DMA request and the DMA controller retrieves the provided data from the SCI Data Register High SCIDRH and SCI Data ...

Page 1250: ...he RDRF flag is 0 If the address mark wake up mode is selected and the received frame has the address bit set the receive data register full flag RDRF in SCI Status Register 1 SCISR1 is set If the receive interrupt enable bit RIE in the SCI Status Register 2 SCISR2 is set the RDRF interrupt request is generated The RWU bit is cleared and the receiver enters the Run state via the wake1 transition I...

Page 1251: ...adjust for baud rate mismatch the cyclic sample counter RSC is re synchronized by reset after successful start bit qualification A start bit is successfully qualified if no reception is ongoing and three consecutive high samples are followed immediately by a low sample Start Bit Verification After the successful start bit qualification the receiver starts to verify the start bit by a two out of th...

Page 1252: ...Table 27 40 27 4 5 3 16 Data Bit Sampling Figure 27 41 Data and Stop Bit Sampling and Strobing 010 Yes Yes 100 Yes Yes 011 No No 101 No No 110 No No 111 No No Table 27 40 Start Bit Noise Detection RS8 RS9 RS10 Noise Detected 000 No 001 Yes 010 Yes 100 Yes 011 Yes 101 Yes 110 Yes 111 Yes Table 27 39 Start Bit Verification continued Result RS3 RS5 RS7 Start Bit Verified Noise Detected Sampled Value ...

Page 1253: ...ode bit SYNM in the SCI Control Register 5 SCICR5 is 0 Data Bit Synchronization Right Shifted Edges This kind of sample counter synchronization happens if the transmitter is slower than the receiver The reset behavior of the sample counter is shown in Figure 27 42 The sample counter reset condition is 1 The data bit N 1 is sampled as 1 and 2 the data bit N is sampled as 0 and 3 a falling edge cons...

Page 1254: ... Bit Synchronization Left Shifted Edges If the 0 sample of the falling edge condition is received at sample 9 or 10 no sample counter synchronization is performed 27 4 5 3 18 Stop Bit Verification The reception of a valid stop bit is verified if at least two out of the sample RS8 RS9 and RS10 are sampled high If this is not that case a framing error is detected Noise is detected if not all of the ...

Page 1255: ...only the OR flag is set All other error flags are not updated If the receiver has not detected an overrun and has detected noise as described in Section 27 4 5 3 13 Bit Sampling the NF flag is set If the receiver has not detected an overrun and has detected a framing error as described in Section 27 4 5 3 13 Bit Sampling the FE flag is set If the receiver has not detected an overrun and has detect...

Page 1256: ...rk Wakeup The address mark wakeup mode is selected when the WAKE bit in SCI Control Register 1 SCICR1 is 1 If the WAKE bit is set the address bit is added to the frame format In this mode the receiver leaves the wakeup state when a data frame with the address bit value of 1 was received This frame is the address frame and contains address information which can be evaluated by the application If th...

Page 1257: ... select both transmitter and receiver reset on bit error detection LIN Control Register 1 LINCTRL1 LDBG 0 select transmission stop on bit error detection SCI Control Register 4 SCICR4 BESTP 1 select transmission DMA stop on bit error detection SCI Control Register 3 SCICR3 BSTP 1 enable both transmitter and receiver SCI Control Register 2 SCICR2 TE 1 SCI Control Register 2 SCICR2 RE 1 27 4 6 2 LIN...

Page 1258: ... 6 3 1 Application Controlled LIN TX Frame generation In this mode the application requests and controls the generation of an LIN TX Frame by subsequent write access to the LIN TX Register LINTX To determine when to write to the LIN TX Register LINTX the application can use the TXRDY flag in the LIN Status Register 1 LINSTAT1 If this flag is set the application can write to the LIN TX Register LIN...

Page 1259: ...is shown in Figure 27 48 The content of the fields in the memory is the same as described in LIN TX Register LINTX TX Frame Figure 27 48 DMA Controlled LIN TX Frame generation 27 4 6 4 LIN RX frame generation The eSCI module supports two modes of LIN RX Frame generation and reception In the application mode the application provides the required data by subsequent write and read accesses to and fro...

Page 1260: ...te fields These data are not transferred into the LIN RX Register LINRX The CRC and Checksum checking is performed internally In case of errors they will be reported as described in Section 27 4 6 5 LIN Error Reporting 27 4 6 4 2 DMA Controlled LIN RX Frames generation In this mode the eSCI module controls the generation of LIN RX frame header and the reception of the frame data automatically and ...

Page 1261: ... bit error flag BERR in the LIN Status Register 2 LINSTAT2 is set In addition the RXRDY flag will also be set the LINRX register must be read before normal operations can proceed 27 4 6 5 3 Standard Bit Error Detection The standard bit error detection is performed on each byte field transmission During the transmission of the frame header and frame data the receiver is running and receives the sig...

Page 1262: ...tions are performed The bit error flag BERR will be set if BESTP is 0 the remainder of the byte will be transmitted normally if BESTP is 1 the remaining bits in the byte after the error bit are transmitted as 1s idle To adjust to different bus loads the sample point at which the incoming bit is compared to the one which was transmitted can be selected with the BESM bit see Figure 27 51 If set the ...

Page 1263: ...he LIN TX Register LINTX RX frame was set the checksum checking is performed based on the received checksum byte The checksum mode is selected by the CSM bit in the LIN TX Register LINTX RX frame If the value received in the checksum bytes did not match the calculated checksum the checksum error flag CKERR in the LIN Status Register 1 LINSTAT1 will be set 27 4 6 5 7 CRC Error Detection The CRC che...

Page 1264: ...p condition on the selected receiver input the LIN wakeup flag LWAKE in the LIN Status Register 1 LINSTAT1 will be set If the LIN debug mode bit LDBG in the LIN Control Register 1 LINCTRL1 is not set the transmitter and receiver will be reset Since each valid wakeup condition violates the byte field structure the frame error flag FE in the SCI Status Register 1 SCISR1 will be set too The eSCI dete...

Page 1265: ...1 SCISR1 is set this indicates the start of transmission the iCMT bit was cleared 3 clear and subsequently set the TE bit in SCI Control Register 2 SCICR2 this set the internal iPRE bit which requests the preamble transmission 4 write to SCI Data Register High SCIDRH and SCI Data Register Low SCIDRL this sets the internal iCMT bit which requests the data transmission The priority scheme of the tra...

Page 1266: ...MPC563XM Reference Manual Rev 1 1266 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 1267: ...ator pin EXTAL The clock source is selected by the CLK_SRC bit in the CTRL register After reset the modules are enabled MDIS bit in MCR register is 0 and in freeze mode bit FRZ and HALT in MCR are set As a consequence the flag bits FRZ_ACK and LPM_ACK are also set in the MCR register The individual filters per message buffer feature is implemented The memory to store the individual filters is impl...

Page 1268: ...ion of the CAN protocol specification Version 2 0 B Ref 1 which supports both standard and extended message frames A flexible number of Message Buffers 16 32 or 64 is also supported The Message Buffers are stored in an embedded RAM dedicated to the FlexCAN module Please refer to the Device User Guide for the actual number of Message Buffer configured in the MCU 288 544 1056 Bus Interface Unit max ...

Page 1269: ...gth Each MB configurable as Rx or Tx all supporting standard and extended messages Individual Rx Mask Registers per Message Buffer Includes either 1056 bytes 64 MBs 544 bytes 32 MBs or 288 bytes 16 MBs of RAM used for MB storage Includes either 256 bytes 64 MBs 128 bytes 32 MBs or 64 bytes 16 MBs of RAM used for individual Rx Mask Registers Full featured Rx FIFO with storage capacity for 6 frames ...

Page 1270: ...serted In this mode transmission is disabled all error counters are frozen and the module operates in a CAN Error Passive mode Ref 1 Only messages acknowledged by another CAN station will be received If FlexCAN detects a message that has not been acknowledged it will flag a BIT0 error without changing the REC as if it was trying to acknowledge the message Loop Back Mode The module enters this mode...

Page 1271: ... is enabled See Section 28 5 9 4 Stop Mode for more information 28 3 External Signal Description 28 3 1 Overview The FlexCAN module has two I O signals connected to the external MCU pins These signals are summarized in Table 28 1 and described in more detail in the next subsections 28 3 2 Signal Descriptions 28 3 2 1 CAN Rx This pin is the receive pin from the CAN bus transceiver Dominant state is...

Page 1272: ... MBs The Rx Global Mask RXGMASK Rx Buffer 14 Mask RX14MASK and the Rx Buffer 15 Mask RX15MASK registers are provided for backwards compatibility and are not used when the BCC bit in MCR is asserted The address ranges 0060 047F and 0880 097F are occupied by two separate embedded memories These two ranges are completely occupied by RAM 1056 and 256 bytes respectively only when FlexCAN is configured ...

Page 1273: ...nning Timer TIMER S U Yes Yes Base 000C Reserved Base 0010 Rx Global Mask RXGMASK S U Yes No Base 0014 Rx Buffer 14 Mask RX14MASK S U Yes No Base 0018 Rx Buffer 15 Mask RX15MASK S U Yes No Base 001C Error Counter Register ECR S U Yes Yes Base 0020 Error and Status Register ESR S U Yes Yes Base 0024 Interrupt Masks 2 IMASK2 S U Yes Yes Base 0028 Interrupt Masks 1 IMASK1 S U Yes Yes Base 002C Interr...

Page 1274: ... 2 Message Buffer Structure Table 28 4 Message Buffer Code for Rx buffers Rx Code BEFORE Rx New Frame Description Rx Code AFTER Rx New Frame Comment 0000 INACTIVE MB is not active MB does not participate in the matching process 0100 EMPTY MB is active and empty 0010 MB participates in the matching process When a frame is received successfully the code is automatically updated to FULL 0010 FULL MB ...

Page 1275: ... AEN bit in MCR is asserted MB does not participate in the arbitration process 0 1100 1000 Transmit data frame unconditionally once After transmission the MB automatically returns to the INACTIVE state 1 1100 0100 Transmit remote frame unconditionally once After transmission the MB automatically becomes an Rx MB with the same ID 0 1010 1010 Transmit a data frame whenever a remote request frame wit...

Page 1276: ...urrent MB has a Remote Frame to be transmitted 0 Indicates the current MB has a Data Frame to be transmitted LENGTH Length of Data in Bytes This 4 bit field is the length in bytes of the Rx or Tx data which is located in offset 8 through F of the MB space see Figure 28 2 In reception this field is written by the FlexCAN module copied from the DLC Data Length Code field of the received frame In tra...

Page 1277: ...ame received and not read yet The region 10 DF is reserved for internal use of the FIFO engine The region E0 FF contains an 8 entry ID table that specifies filtering criteria for accepting frames into the FIFO Figure 28 4 shows the three different formats that the elements of the ID table can assume depending on the IDAM field of the MCR Note that all elements of the table must have the same forma...

Page 1278: ...d RXIDB_0 RXIDB_1 Rx Frame Identifier Format B Specifies an ID to be used as acceptance criteria for the FIFO In the standard frame format the 11 most significant bits a full standard ID 3 to 13 are used for frame identification In the extended frame format all 14 bits of the field are compared to the 14 most significant bits of the received ID RXIDC_0 RXIDC_1 RXIDC_2 RXIDC_3 Rx Frame Identifier F...

Page 1279: ...d at MCU level When FRZ is asserted FlexCAN is enabled to enter Freeze Mode Negation of this bit field causes FlexCAN to exit from Freeze Mode 1 Enabled to enter Freeze Mode 0 Not enabled to enter Freeze Mode FEN FIFO Enable This bit controls whether the FIFO feature is enabled or not When FEN is set MBs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory r...

Page 1280: ... Up Interrupt generation 1 Wake Up Interrupt is enabled 0 Wake Up Interrupt is disabled SOFT_RST Soft Reset When this bit is asserted FlexCAN resets its internal state machines and some of the memory mapped registers The following registers are reset MCR except the MDIS bit TIMER ECR ESR IMASK1 IMASK2 IFLAG1 IFLAG2 Configuration registers that control the interface to the CAN bus are not affected ...

Page 1281: ... Mode or Stop Mode If this bit had been asserted by the time FlexCAN entered Doze Mode or Stop Mode then FlexCAN will look for a recessive to dominant transition on the bus during these modes If a transition from recessive to dominant is detected during Doze Mode FlexCAN resumes its clocks and if enabled to do so generates a Wake Up interrupt to the CPU If a transition from recessive to dominant i...

Page 1282: ...lexCAN is not enabled to enter low power mode when Doze Mode is requested SRX_DIS Self Reception Disable This bit defines whether FlexCAN is allowed to receive frames transmitted by itself If this bit is asserted frames transmitted by the module will not be stored in any MB regardless if the MB is programmed with an ID that matches the transmitted frame and no interrupt flag or interrupt signal wi...

Page 1283: ... field they are all the same format See Section 28 4 3 Rx FIFO Structure MAXMB Maximum Number of Message Buffers This 6 bit field defines the maximum number of message buffers that will take part in the matching and arbitration processes The reset value 0F is equivalent to 16 MB configuration This field should be changed only while the module is in Freeze Mode Maximum MBs in use MAXMB 1 NOTE MAXMB...

Page 1284: ...k frequency PRESDIV 1 RJW Resync Jump Width This 2 bit field defines the maximum number of time quanta1 that a bit time can be changed by one re synchronization The valid programmable values are 0 3 Resync Jump Width RJW 1 PSEG1 Phase Segment 1 This 3 bit field defines the length of Phase Buffer Segment 1 in the bit time The valid programmable values are 0 7 Phase Buffer Segment 1 PSEG1 1 x Time Q...

Page 1285: ... may use only the PLL clock feeding the FlexCAN module In these cases this bit has no effect on the module operation TWRN_MSK Tx Warning Interrupt Mask This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is negated 1 Tx Warning Interrupt...

Page 1286: ...e BOFF_REC bit had never been asserted If the negation occurs after 128 sequences of 11 recessive bits occurred then FlexCAN will re synchronize to the bus by waiting for 11 recessive bits before joining the bus After negation the BOFF_REC bit can be re asserted again during Bus Off but it will only be effective the next time the module enters Bus Off If BOFF_REC was negated when the module entere...

Page 1287: ...bit free running counter that can be read and written by the CPU The timer starts from 0000 after Reset counts linearly to FFFF and wraps around The timer is clocked by the FlexCAN bit clock which defines the baud rate on the CAN bus During a message transmission reception it increments by one for each bit that is received or transmitted When there is no message on the bus it counts using the prev...

Page 1288: ...masks The contents of this register must be programmed while the module is in Freeze Mode and must not be modified when the module is transmitting or receiving frames Figure 28 8 Rx Global Mask Register RXGMASK MI31 MI0 Mask Bits For normal Rx MBs the mask bits affect the ID filter programmed on the MB For the Rx FIFO the mask bits affect all bits programmed in the filter table ID IDE RTR Base 000...

Page 1289: ...Identifier in Message Buffer 15 When the FEN bit in MCR is set FIFO enabled the RXG14MASK also applies to element 7 of the ID filter table This register has the same structure as the Rx Global Mask Register It must be programmed while the module is in Freeze Mode and must not be modified when the module is transmitting or receiving frames Address Offset 18 Reset Value FFFF_FFFF 28 4 4 7 Error Coun...

Page 1290: ...et to zero At any instance of dominant bit following a stream of less than 11 consecutive recessive bits the internal counter resets itself to zero without affecting the Tx_Err_Counter value If during system start up only one node is operating then its Tx_Err_Counter increases in each message it is trying to transmit as a result of acknowledge errors indicated by the ACK_ERR bit in the Error and S...

Page 1291: ..._INT bit is set when the RX_WRN flag transition from 0 to 1 meaning that the Rx error counters reached 96 If the corresponding mask bit in the Control Register RWRN_MSK is set an interrupt is generated to the CPU This bit is cleared by writing it to 1 Writing 0 has no effect 1 The Rx error counter transition from 96 to 96 0 No such occurrence BIT1_ERR Bit1 Error This bit indicates when an inconsis...

Page 1292: ...ferent from the received 1 A CRC error occurred since last read of this register 0 No such occurrence FRM_ERR Form Error This bit indicates that a Form Error has been detected by the receiver node i e a fixed form bit field contains at least one illegal bit 1 A Form Error occurred since last read of this register 0 No such occurrence STF_ERR Stuffing Error This bit indicates that a Stuffing Error ...

Page 1293: ...Control Register BOFF_MSK is set an interrupt is generated to the CPU This bit is cleared by writing it to 1 Writing 0 has no effect 1 FlexCAN module entered Bus Off state 0 No such occurrence ERR_INT Error Interrupt This bit indicates that at least one of the Error Bits bits 16 21 is set If the corresponding mask bit in the Control Register ERR_MSK is set an interrupt is generated to the CPU This...

Page 1294: ... a range of 32 Message Buffer Interrupts It contains one interrupt mask bit per buffer enabling the CPU to determine which buffer generates an interrupt after a successful transmission or reception i e when the corresponding IFLAG1 bit is set Figure 28 12 Interrupt Masks 1 Register IMASK1 Base 0024 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BUF 63M BUF 62M BUF 61M BUF 60M BUF 59M BUF 58M BUF 57M BUF ...

Page 1295: ... 2 Register IFLAG2 BUF32I BUF63I Buffer MBi Interrupt Each bit flags the respective FlexCAN Message Buffer MB32 to MB63 interrupt 1 The corresponding buffer has successfully completed transmission or reception 0 No such occurrence 28 4 4 12 Interrupt Flags 1 Register IFLAG1 This register defines the flags for 32 Message Buffer interrupts and FIFO interrupts It contains one interrupt flag bit per b...

Page 1296: ...the FIFO is enabled this flag indicates that 4 out of 6 buffers of the FIFO are already occupied FIFO almost full 1 MB6 completed transmission reception or FIFO almost full 0 No such occurrence BUF5I Buffer MB5 Interrupt or Frames available in FIFO If the FIFO is not enabled this bit flags the interrupt for MB5 If the FIFO is enabled this flag indicates that at least one frame is available to be r...

Page 1297: ...essage Buffer feature may not be available in low cost MCUs Please consult the specific MCU documentation to find out if this feature is supported If not supported the RXGMASK RX14MASK and RX15MASK registers are available regardless of the value of the BCC bit Figure 28 15 Rx Individual Mask Registers RXIMR0 RXIMR63 MI31 MI0 Mask Bits For normal Rx MBs the mask bits affect the ID filter programmed...

Page 1298: ... Message Buffer for transmission by executing the following procedure If the MB is active transmission pending write an ABORT code 1001 to the Code field of the Control and Status word to request an abortion of the transmission then read back the Code field and the IFLAG register to check if the transmission was aborted see Section 28 5 6 1 Transmission Abort Mechanism If backwards compatibility i...

Page 1299: ...etermine the priority of transmission If two or more MBs have the same priority 3 extra bits and the same regular ID the lowest MB will be transmitted first Once the highest priority MB is selected it is transferred to a temporary storage space called Serial Message Buffer SMB which has the same structure as a normal MB but is not user accessible This operation is called move out and after it is d...

Page 1300: ...cked unless the CPU reads the C S word of another MB Note that only a single MB is locked at a time The only mandatory CPU read operation is the one on the Control and Status word to assure data coherency see Section 28 5 6 Data Coherence The CPU should synchronize to frame reception by the status flag bit for the specific MB in one of the IFLAG Registers and not by the Code field of that MB Polli...

Page 1301: ...not locked see Section 28 5 6 3 Message Buffer Lock Mechanism The Code field is either EMPTY or else it is FULL or OVERRUN but the CPU has already serviced the MB read the C S word and then unlocked the MB If the first MB with a matching ID is not free to receive the new frame then the matching algorithm keeps looking for another free MB until it finds one If it can not find one that is free then ...

Page 1302: ...ed NOTE The individual Rx Mask per Message Buffer feature may not be available in low cost MCUs Please consult the specific MCU documentation to find out if this feature is supported If not supported the RXGMASK RX14MASK and RX15MASK registers are available regardless of the value of the BCC bit 28 5 6 Data Coherence In order to maintain data coherency and FlexCAN proper operation the CPU must obe...

Page 1303: ...s set the frame was transmitted If the corresponding IFLAG is reset the CPU must wait for it to be set and then the CPU must read the CODE field to check if the MB was aborted CODE 1001 or it was transmitted CODE 1000 28 5 6 2 Message Buffer Deactivation Deactivation is mechanism provided to maintain data coherence when the CPU writes to the Control and Status word of active MBs out of Freeze Mode...

Page 1304: ...Suppose for example that the FIFO is disabled and the second and the fifth MBs of the array are programmed with the same ID and FlexCAN has already received and stored messages into these two MBs Suppose now that the CPU decides to read MB number 5 and at the same time another message with the same ID is arriving When the CPU reads the Control and Status word of MB number 5 this MB is locked The n...

Page 1305: ...provided to accept only frames intended for the target application thus reducing the interrupt servicing work load The filtering criteria is specified by programming a table of 8 32 bit registers that can be configured to one of the following formats see also Section 28 4 3 Rx FIFO Structure Format A 8 extended or standard IDs including IDE and RTR Format B 16 standard IDs or 16 extended 14 bit ID...

Page 1306: ...or not For format C remote frames are always accepted if they match the ID 28 5 8 2 Overload Frames FlexCAN does transmit overload frames due to detection of following conditions on CAN bus Detection of a dominant bit in the first second bit of Intermission Detection of a dominant bit at the 7th bit last of End of Frame field Rx frames Detection of a dominant bit at the 8th bit last of Error Frame...

Page 1307: ...SDIV PROPSEG PSEG1 PSEG2 and RJW See Section 28 4 4 2 Control Register CTRL The PRESDIV field controls a prescaler that generates the Serial Clock Sclock whose period defines the time quantum used to compose the CAN waveform A time quantum is the atomic unit of time handled by the CAN engine A bit time is subdivided into three segments1 reference Figure 28 17 and Table 28 8 SYNC_SEG This segment h...

Page 1308: ...cts transitions to occur on the bus during this period Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point Sample Point A node samples the bus at this point If the three samples per bit option is selected then this point marks the position of the third sample Table 28 9 CAN Standard Compliant Bit Time Segment Settings Time Segment 1 Time Segment 2 Re synchroni...

Page 1309: ...er than the oscillator clock frequency i e the PLL can not be programmed to divide down the oscillator clock There must be a minimum ratio between the peripheral clock frequency and the CAN bit rate as specified in Table 28 10 A direct consequence of the first requirement is that the minimum number of time quanta per CAN bit must be 8 so the oscillator clock frequency should be at least 8 times th...

Page 1310: ...e executing any other action otherwise FlexCAN may operate in an unpredictable way In Freeze mode all memory mapped registers are accessible Exiting Freeze Mode is done in one of the following ways CPU negates the FRZ bit in the MCR Register The MCU is removed from Debug Mode and or the HALT bit is negated Once out of Freeze Mode FlexCAN tries to re synchronize to the CAN bus by waiting for 11 con...

Page 1311: ...and drives its Tx pin as recessive Shuts down the clocks to the CPI and MBM sub modules Sets the NOT_RDY and LPM_ACK bits in MCR The Bus Interface Unit continues to operate enabling the CPU to access memory mapped registers except the Free Running Timer the Error Counter Register and the Message Buffers which can not be accessed in Doze Mode Exiting Doze Mode is done in one of the following ways C...

Page 1312: ...of Intermission and checks it to be recessive Waits for all internal activities like arbitration matching move in and move out to finish Ignores its Rx input pin and drives its Tx pin as recessive Sets the NOT_RDY and LPM_ACK bits in MCR Sends a Stop Acknowledge signal to the CPU so that it can shut down the clocks globally Exiting Stop Mode is done in one of the following ways CPU resuming the cl...

Page 1313: ...successful transmission reception and is cleared when the CPU writes it to 1 unless another interrupt is generated at the same time NOTE It must be guaranteed that the CPU only clears the bit causing the current interrupt For this reason bit manipulation instructions BSET must not be used to clear interrupt flags These instructions may cause accidental clearing of interrupt flags which are set aft...

Page 1314: ...ons for initializing the FlexCAN module 28 6 1 FlexCAN Initialization Sequence The FlexCAN module may be reset in three ways MCU level hard reset which resets all memory mapped registers asynchronously MCU level soft reset which resets some of the memory mapped registers synchronously refer to Table 28 2 to see what registers are affected by soft reset SOFT_RST bit in MCR which has the same effect...

Page 1315: ...nitialized If FIFO was enabled the 8 entry ID table must be initialized Other entries in each Message Buffer should be initialized as required Initialize the Rx Individual Mask Registers Set required interrupt mask bits in the IMASK Registers for all MB interrupts in CTRL Register for Bus Off and Error interrupts and in MCR Register for Wake Up interrupt Negate the HALT bit in MCR Starting with th...

Page 1316: ...MPC563XM Reference Manual Rev 1 1316 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 1317: ...le PIT RTI 32 bit counter Four Timer Channels One Real Time Interrupt RTI timer channel clocked from the crystal oscillator that can be used to wake the part from stop mode The counter period of a running timer can be modified by first disabling the timer setting a new load value and then enabling the timer again see Figure 29 8 In the case of the RTI because of the different clock domains system ...

Page 1318: ...provides a dedicated Real Time Interrupt Timer RTI which runs on a separate clock and can be used for system wakeup 29 2 2 Features The main features of this block are One RTI Real Time Interrupt timer to wakeup the CPU in stop mode Timers can generate DMA trigger pulses Timers can generate interrupts All interrupts are maskable RTI interrupt can be raised even when the bus clock is switched off R...

Page 1319: ...al Description The PIT module has no external pins 29 5 Memory Map and Register Description This section provides a detailed description of all registers accessible in the PIT_RTI module 29 5 1 Memory Map Table 29 1 gives an overview on all PIT_RTI registers Table 29 1 PIT_RTI Memory Map Address Offset Use Access 0x000 PIT Module Control Register R W 0x004 0x0EC Reserved R 0x0F0 0x0FC RTI Channel ...

Page 1320: ...ed at the module level NOTE Reserved registers will read as 0 writes will have no effect 29 5 2 Register Descriptions This section describes in address order all the PIT_RTI registers and their individual bits NOTE The RTI registers should be programmed only when the RTI clock is running channel 0x08 Timer Control Register R W channel 0x0C Timer Flag Register R W Table 29 2 continued Timer Channel...

Page 1321: ... 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 MDIS _RTI MDIS FRZ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29 2 PIT Module Control Registers PITMCR Field Description MDIS_RTI Module Disable RTI section This is used to disable the RTI timer This bit should be enabled b...

Page 1322: ...0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29 3 Timer Load Value Register LDVAL Table 29 4 LDVAL Field Descriptions Field Description TSVn Time Start Value Bits These bits set the timer start value The timer will count down until it reaches 0 then it will generate an interrupt and load this register value again Writing a new value to this register will not restart the timer instead the value...

Page 1323: ...L18 TVL17 TVL16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TVL15 TVL14 TVL13 TVL12 TVL11 TVL10 TVL9 TVL8 TVL7 TVL6 TVL5 TVL4 TVL3 TVL2 TVL1 TVL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29 4 Current Timer Value Register CVAL Table 29 5 CVAL Field Descriptions Field Description TVLn Current Timer Value These bits represent the current timer value...

Page 1324: ...2 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE TEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29 5 Timer Control Register TCTRL Table 29 6 TCTRL Field Descriptions Field Description TIE Timer Interrupt Enable Bit 0 Interrupt requests from Timer x are disabled 1 Interrupt will be requested whenever TIF is set When an interrupt is pending TIF set enabling the interrupt will immed...

Page 1325: ...RL registers A new interrupt can be generated only after the previous one is cleared Since in the case of the RTI clearing the interrupt crosses clock domains a minimum load value of 32 should be maintained If desired the current counter value of the timer can be read via the CVAL registers The value of the RTI counter can be delayed considerably as it is synchronized to the bus clock from the RTI...

Page 1326: ...9 8 Modifying Running Timer Period Figure 29 9 Dynamically Setting a New Load Value 29 6 1 2 Debug Mode In Debug Mode the timers will be frozen this is intended to aid software development allowing the developer to halt the processor investigate the current state of the system e g the timer values and then continue the operation 29 6 2 Interrupts All of the timers support interrupt generation The ...

Page 1327: ... every 30 ms First the PIT module needs to be activated by writing a 0 to the MDIS bit in the PITCTRL register The 50 MHz clock frequency equates to a clock period of 20 ns and the 10 MHz frequency equates to a clock period of 100 ns Therefor the RTI timer needs to trigger every 500 ms 100 ns 5000000 cycles Timer 1 needs to trigger every 5 12 ms 20 ns 256000 cycles and timer 3 every 30 ms 20 ns 15...

Page 1328: ...eliminary Subject to Change Without Notice Timer 1 PIT_LDVAL1 0x0003E7FF setup timer 1 for 256000 cycles PIT_TCTRL1 TIE enable Timer 1 interrupts PIT_TCTRL1 TEN start timer 1 Timer 3 PIT_LDVAL3 0x0016E35F setup timer 3for 1500000 cycles PIT_TCTRL3 TEN start timer 3 ...

Page 1329: ...ply of the regulators VDDREG There is no requirement for special power up or down sequencing required VDDREG can be tied to VSS to bypass the 3 3V and 1 2V internal regulators Regulators and power supply LVI POR control blocks use a precision bandgap voltage reference A low impedance buffered version of the absolute and curvature corrected bandgap voltage reference is available to be measured usin...

Page 1330: ...3p3 POR vdd1p2 REG1p2ref POR vddreg REG 3p3ref POR vddreg VBGref LVI3p3ref LVI1p2ref LVI1p0ref REG3p3ref REG1p2ref LVI VREG Reference LVI5 vddreg LVI3 vddeh LVI3 vdd3p3 LVI1 2 vdd1p2 LVI1 0 vdd1p2 POR5 vddreg POR3 vddeh POR3 vdd3p3 POR1 2 vdd1p2 Vreg1p2 Vreg3p3 Digital Interface Configuration and Status Register Trimming Register POR vddeh POR vdd3p3 POR_vdd1p2 LVI vddreg LVI vddeh LVI vdd3p3 LVI ...

Page 1331: ...grounding VDDREG In this case external regulation and low voltage control must be supplied 30 2 1 2 VDDEH Power supply input 5V or 3 3V nominal taken from one of the pad ring I O segment which is near the voltage regulator Table 30 1 Power Management Controller External Signals Name Type Voltage Description VDDREG Supply 4 0 5 5V Power supply for the voltage regulator VDDEH Supply 2 7 5 5V Power s...

Page 1332: ...acitor for each pin that supplies the digital core is 20uF 100uF with very low ESR max 10 mOhm A ceramic capacitor is also desirable with 200 nF to 1uF capacitance When switching current load is lower it is possible to reduce the requirements of the bypass capacitor to 1uF 5 uF and 100 mOhm ESR 30 2 1 5 VRC1p2 1 2V regulator output that drives the base of the external NPN transistor 30 3 Memory Ma...

Page 1333: ...pply does not cause system reset 2 LVI5R 5V LVI reset enable This bit defines whether an LVI assertion on the 5V supply of the voltage regulator VDDREG will generate system reset or not 0 Reset LVI assertion on the 5V supply of the voltage regulator causes system reset 1 Interrupt LVI assertion on the 5V supply of the voltage regulator does not cause system reset 3 LVI3R 3 3V LVI reset enable This...

Page 1334: ...errupt request is disabled 1 Enabled LVI interrupt request is enabled 11 LVI3E 3 3V LVI enable This bit enables the generation of the LVI interrupt request when the 3 3V power supply gets below the corresponding LVI threshold The LVI interrupt is independent from LVI reset If both interrupt and reset are enabled then reset and interrupt will be generated but reset will then clear the interrupt 0 D...

Page 1335: ...V12TRIM LVI12TRIM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 4 Trimming Register TRIMR Table 30 4 TRIMR Field Descriptions Field Description 0 11 Reserved should be cleared 12 15 LVI50TRI M LVI 5V trimming This field is used to fine tune the voltage threshold of the 5V rising LVI which is used to monitor the VDDREG supply Nominal configuration 0111 4 43V 0110 4 41V 0101 4 39V 0100 4 37V 001...

Page 1336: ...6V 1110 3 33V 1101 3 30V 1100 3 27V 1011 3 24V 1010 3 21V 1001 3 18V 1000 3 15V 20 23 LVI33TRI M LVI 3 3V trimming This field is used to fine tune the voltage threshold of the 3 3V rising LVI which is used to monitor the 3 3V regulated output and the VDDEH supply Nominal configuration 0111 3 14V 0110 3 12V 0101 3 10V 0100 3 08V 0011 3 06V 0010 3 04V 0001 3 02V 0000 3 00V Default 1111 2 98V 1110 2 ...

Page 1337: ...l configuration 0111 1 41V 0110 1 39V 0101 1 37V 0100 1 35V 0011 1 33V 0010 1 31V 0001 1 29V 0000 1 27V Default 1111 1 25V 1110 1 23V 1101 1 21V 1100 1 19V 1011 1 17V 1010 1 15V 1001 1 13V 1000 1 11V 28 31 LVI12TRI M LVI 1 2V trimming This field is used to fine tune the voltage threshold of the 1 2V rising LVI Nominal configuration 0111 1 22V 0110 1 20V 0101 1 18V 0100 1 16V 0011 1 14V 0010 1 12V ...

Page 1338: ... regulator switch Software can clear this bit by writing 1 to it 0 No brown out detected 1 Brown out detected 6 BGS1 Bandgap Status1 This read only bit gets asserted when the bandgap circuit has finished its startup procedure during power up The LVIs are disabled output negated while BGS1 is negated 0 Bandgap not ready LVIs disabled 1 Bandgap ready LVIs enabled 7 BGS2 Bandgap Status 2 This read on...

Page 1339: ...ars the LVI1F flag 21 23 Reserved 24 LVIRF Reset pin supply LVI flag This read only bit is the LVI interrupt flag associated with the supply of the I O segment that contains the reset pin It is asserted when the supply falls below the corresponding LVI threshold and can be cleared by the CPU by writing 1 to the LVIRC bit If the LVIRE bit is also asserted an LVI interrupt is sent to the CPU If LVIR...

Page 1340: ...G is grounded as long as VDDEH or VDD3p3 are at the correct voltage 30 4 1 Bandgap The bandgap voltage of the PMC is capable of generating a reference voltage of 1 219V that varies by 4 before calibration and 1 after calibration over temperature and lifetime It is used as reference to generate all supply voltages for this reason it is powered directly out of the 5V domain to avoid startup racing c...

Page 1341: ...or is connected internally to the 5V supply that feeds the voltage regulator VDDREG The output of the LVI goes to logical 1 when the monitored voltage rises above the LVI rising trip point Maximum hysteresis value between rising and falling trip points is 90 mV In case the monitored voltage falls below the nominal trip point the LVI output goes to logical 0 The assertion and negation voltages are ...

Page 1342: ... 3V supply is 6 including line and load variation The regulator output voltage is adjustable via software by writing to the V33TRIM field of the TRIMR register which selects one of the 16 voltages available through the appropriate tapped output of a 24 leg resistor chain centered in 3 39V The taps are set between 3 15V and 3 60V at 30mV intervals Metal options are available to map the 16 selection...

Page 1343: ...ad The LVIs can be programmed to trigger power on reset enabled by default If programmed to generate reset the monitors are able to hold reset from 3 3V POR until greater or equal to LVI threshold 30 4 5 1 2V Voltage Regulator Controller A voltage regulator controller is used to source up to 20 mA of base current to an external NPN transistor which operates as an emitter follower The 1 2V supply i...

Page 1344: ...lt If programmed to generate reset the monitor is able to hold reset from 1 2V POR until greater or equal to LVI threshold 30 4 7 LVI 1 0V A low voltage monitor LVI 1 0V is connected to the 1 2V supply The output of the LVI goes to logical 1 when the monitored voltage rises above the rising trip point around 0 85V Nominal hysteresis value between rising and falling levels is 40 mV In case the moni...

Page 1345: ...LVI on VDDREG is summarized in Figure 30 8 As shown the LVI will reach a consistent state before the POR actually releases the reset avoiding false startup condition The PORs for each power supply are not intended to indicate that the power supply has dropped below the specified voltage range for the device The 1 2V and the 3 3V supplies are monitored respectively by the LVI 1 2V and LVI 3 3V circ...

Page 1346: ...enerating a single power on reset output signal which can be distributed throughout the SoC 30 4 8 2 ADC Test Mux During PMC functional mode it is possible to perform direct measurements through the ADC bandgap reference LVI references and sampling voltages Vreg1p2 Vreg3p3 voltage references For any LVI Table 30 9 Power on reset bar thresholds Power on reset threshold Min Typ Max POR_B 1 2 rising ...

Page 1347: ...becomes asserted 30 5 Application Information 30 5 1 Regulator Example Figure 30 9 Regulator Hookup 30 5 2 Recommended Power Transistors The following NPN transistors are recommended for use with the on chip voltage regulator controller ON SemiconductorTM BCP68T1 or NJD2873 as well as Philips SemiconductorTM BCP68 The collector of the external transistor must be connected to the same voltage suppl...

Page 1348: ...MPC563XM Reference Manual Rev 1 1348 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 1349: ...s for the Device Identification Register on this device 31 1 3 Unavailable Instructions The following instructions are not available on this device TEST_LEAKAGE ENABLE_TEST_CTRL RUN_PLLBIST Table 31 1 Device Specific Parameters Parameter Value Number of JCOMP bits used 1 Length of the boundary scan chain path for the device 464 Number of auxiliary TAP controllers that share the TAP with the JTAGC ...

Page 1350: ...lity and connectivity while remaining transparent to system logic when not in test mode Testing is performed via a boundary scan technique as Table 31 3 Device Specific Auxiliary TAP Controller Instructions Instruction Code 4 0 Instruction Summary ACCESS_AUX_TAP_NPC 10000 Enables access to the NPC TAP controller ACCESS_AUX_TAP_ONCE 10001 Enables access to the e200z335 OnCE TAP controller ACCESS_AU...

Page 1351: ...ode 31 2 3 1 Reset The JTAGC block is placed in reset when either power on reset is asserted JCOMP is negated or the TMS input is held high for enough consecutive rising edges of TCK to sequence the TAP controller state machine into the Test Logic Reset state Holding TMS high for 5 consecutive rising edges of TCK guarantees entry into the Test Logic Reset state regardless of the current TAP contro...

Page 1352: ...s of 5 signals that connect to off chip development tools and allow access to test support functions The JTAGC signals are outlined in Table 31 4 31 3 2 Detailed Signal Descriptions This section describes each of the signals listed in Table 31 4 in more detail 31 3 2 1 TCK Test Clock Input Test Clock Input TCK is an input pin used to synchronize the test logic and control register access through t...

Page 1353: ...isters accessible through the TAP interface including data registers and the instruction register Individual bit level descriptions and reset states of each register are included These registers are not memory mapped and can only be accessed through the TAP 31 4 1 Register Descriptions The JTAGC block registers are described in this section 31 4 1 1 Instruction Register The JTAGC block uses a 5 bi...

Page 1354: ...r is selected loads the IDCODE into the shift register to be shifted out on TDO in the Shift DR state No action occurs in the Update DR state The part revision number PRN and part identification number PIN fields are system plugs and the manufacturer identity code MIC is a constant value assigned to the manufacturer by the JEDEC The shift register LSB is forced to logic 1 on the rising edge of TCK...

Page 1355: ...llel hold register bits CENSOR_CTRL correspond directly to the JTAGC output control signals jtag_censor_ctrl L 1 0 The jtag_censor_ctrl signals are used to control chip dependent censorship features Once the ENABLE_CENSOR_CTRL instruction is executed jtag_censor_ctrl will remain valid until a JTAGC reset occurs Figure 31 4 CENSOR_CTRL Register CENSOR_CTRL Censorship Control The CENSOR_CTRL bits ar...

Page 1356: ...ction For more detail on TAP sharing via JTAGC instructions refer to Section 31 5 4 7 ACCESS_AUX_TAP_x Instructions Data is shifted between TDI and TDO though the selected register starting with the least significant bit as illustrated in Figure 31 5 This applies for the instruction register test data registers and the bypass register Figure 31 5 Shifting Data Through a Register 31 5 3 TAP Control...

Page 1357: ...TEST LOGIC RESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 NOTE The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK ...

Page 1358: ...minated once the required number of bits have been acquired 31 5 4 JTAGC Block Instructions The JTAGC block implements the IEEE 1149 1 2001 defined instructions listed in Table 31 5 This section gives an overview of each instruction refer to the IEEE 1149 1 2001 standard for more details All undefined opcodes are reserved Table 31 5 JTAG Instructions Instruction Code 4 0 Instruction Summary IDCODE...

Page 1359: ...register cells on the falling edge of TCK in the Update DR state The data is applied to the external output pins by the EXTEST or CLAMP instruction System operation is not affected 31 5 4 3 SAMPLE Instruction The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register cells at the output pins This sampling ...

Page 1360: ...fficiency by reducing the overall shift path when no test operation of the MCU is required This allows more rapid movement of test data to and from other components on a board that are required to perform test functions While the BYPASS instruction is active the system logic operates normally 31 5 5 Boundary Scan The boundary scan technique allows signals at component boundaries to be controlled a...

Page 1361: ...o Change Without Notice To initialize the JTAGC block and enable access to registers the following sequence is required 5 Set the JCOMP signal to the JTAGC enable value thereby enabling the JTAGC TAP controller 6 Load the appropriate instruction for the test or action to be performed ...

Page 1362: ...MPC563XM Reference Manual Rev 1 1362 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 1363: ...his device Nexus double data rate DDR mode The following bits in the Port Configuration Register DDR_EN LP_DBG LP2_SYN LP1_SYN Table 32 1 Device Parameter Values Parameter Value Number of Nexus trace clients on the device sharing the Nexus auxiliary port not including the NPC 1 SRC ID for e200z335 core 0000 Number of MDO pins available in reduced port mode 4 Number of MDO pins available in full po...

Page 1364: ...cific Parameters Figure 32 1 Nexus Port Controller Block Diagram 32 2 1 Overview On a system on a chip device there are often multiple blocks that require development support Each of these blocks implements a development interface based on the IEEE ISTO 5001 2001 standard The blocks share input and output ports that interface with the development tool The NPC controls the usage of the input and ou...

Page 1365: ...not set for Nexus access or the TAP controller state machine is in the Test Logic Reset state Holding TMS high for 5 consecutive rising edges of TCK guarantees entry into the Test Logic Reset state regardless of the current TAP controller state Asserting power on reset or setting JCOMP to a value other than the value required to enable the NPC block results in asynchronous entry into the reset sta...

Page 1366: ... parameter is given a variable name that is used in the rest of the document Table 32 2 Device Specific Parameters Parameter Variable Name Description FPM_MDO F Number of MDO pins used for message transmission in full port mode This value should be the same for all the Nexus blocks sharing the port RPM_MDO R Number of MDO pins used for message transmission in reduced port mode This value should be...

Page 1367: ...status indication The EVTO output of the NPC is generated based on the values of the individual EVTO signals from all Nexus blocks that implement the signal 32 3 2 2 JCOMP JTAG Compliancy The JCOMP signal provides the ability to share the TAP The NPC TAP controller is enabled when JCOMP is set to the NPC enable encoding otherwise the NPC TAP controller remains in reset Table 32 3 NPC Signal Proper...

Page 1368: ... TDO pin transmits serial output for instructions and data TDO is three stateable and is actively driven in the SHIFT IR and SHIFT DR controller states TDO is updated on the falling edge of TCK and sampled by the development tool on the rising edge of TCK 32 3 2 8 TMS Test Mode Select Test Mode Select Input TMS pin is used to sequence the IEEE 1149 1 2001 TAP controller state machine TMS is sample...

Page 1369: ...YPASS or unimplemented instructions Instructions are shifted in through TDI while the TAP controller is in the Shift IR state and latched on the falling edge of TCK in the Update IR state The latched instruction value can only be changed in the Update IR and Test Logic Reset TAP controller states Synchronous entry into the Test Logic Reset state results in synchronous loading of the BYPASS instruc...

Page 1370: ...t d 0 0 0 0 0 0 0 1 1 1 0 1 Reserved Table 32 5 DID Field Descriptions Bit Name Description 31 2 8 PRN Part Revision Number These bits contain the revision number of the part 27 2 2 DC Design Center These bits indicate the device design center 21 1 2 PIN Part Identification Number These bits contain the part number of the device 11 1 MIC Manufacturer Identity Code These bits contain the reduced Jo...

Page 1371: ...lts Register index 127 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R FPM MCK O_GT MCK O_EN MCKO_DIV EVT_ EN DDR_ EN 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LP_D BG 0 0 0 0 0 LP2_ SYN LP1_ SYN 0 0 0 0 0 0 0 PSTA T_EN W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Table 32 6 PCR Field Descriptions Bit Name Description 31 FPM Full Port Mod...

Page 1372: ... Power Debug Enable This bit enables debug functionality on exit from low power modes on supported devices 1 Low power debug enabled 0 Low power debug disabled 14 1 0 Reserved 9 8 LPn_SYN Low Power Mode n Synchronization These bits are used to synchronize the entry into low power modes between the device and debug tool Supported devices set these bits before a pending entry into low power mode Aft...

Page 1373: ...nicates with each of the Nexus modules and arbitrates for access to the port 32 5 2 1 Output Message Protocol The protocol for transmitting messages via the auxiliary port is accomplished with the MSEO functions The MSEO pins are used to signal the end of variable length packets and the end of messages They are not required to indicate the end of fixed length packets MDO and MSEO are sampled on th...

Page 1374: ... also be sent out serially through TDO Table 32 9 describes the device ID and port replacement output messages that the NPC can transmit on the auxiliary port The TCODE is the first packet transmitted Table 32 9 NPC Output Messages Message Name Min Packet Size bits Max Packet Size bits Packet Type Packet Name Packet Description Device ID Message 6 6 fixed TCODE Value 1 32 32 fixed ID DID register ...

Page 1375: ...elds must end on a port boundary When a variable length field is sized such that it does not end on a port boundary it is necessary to extend and zero fill the remaining bits after the highest order bit so that it can end on a port boundary Multiple fixed length packets may start and or end on a single clock When any packet follows a variable length packet it must start on a port boundary The fiel...

Page 1376: ...plemented by the NPC TAP controller are listed in Table 32 10 The value of the NEXUS ENABLE instruction is 0b0000 Each unimplemented instruction acts like the BYPASS instruction The size of the NPC instruction register is 4 bits Data is shifted between TDI and TDO starting with the least significant bit as illustrated in Figure 32 8 This applies for the instruction register and all Nexus tool mapp...

Page 1377: ...T LOGIC RESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 NOTE The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK ...

Page 1378: ...LECT IR SCAN path and loaded in the UPDATE IR state At this point the Nexus controller state machine shown in Figure 32 10 transitions to the REG_SELECT state The Nexus controller has three states idle register select and data access Table 32 11 illustrates the IEEE 1149 1 sequence to load the NEXUS ENABLE instruction Figure 32 10 NEXUS Controller State Machine Table 32 11 Loading NEXUS ENABLE ins...

Page 1379: ...ding a register there is no requirement to shift out the entire register contents Shifting may be terminated once the required number of bits have been acquired Table 32 12 illustrates a sequence which writes a 32 bit value to a register MSB LSB 7 bit register index R W Figure 32 11 IEEE 1149 1 Controller Command Input Table 32 12 Write to a 32 Bit Nexus Client Register Clock TMS IEEE 1149 1 State...

Page 1380: ... To enable gating of MCKO the MCKO_GT bit in the PCR is written to a logic 1 When enabled nex_mcko_g_ctrl will negate anytime the NPC is in enabled mode but not actively transmitting messages on the auxiliary output port indicating to the MCKO generation logic that MCKO can be gated at this time 32 5 6 EVTO Sharing The NPC block controls sharing of the EVTO output between all Nexus clients that pr...

Page 1381: ...US ENABLE instruction To write control data to NPC tool mapped registers the following sequence is required 1 Write the 7 bit register index and set the write bit to select the register with a pass through the SELECT DR SCAN path in the TAP controller state machine 2 Write the register value with a second pass through the SELECT DR SCAN path Note that the prior value of this register is shifted ou...

Page 1382: ...MPC563XM Reference Manual Rev 1 1382 Freescale Semiconductor Preliminary Subject to Change Without Notice ...

Page 1383: ...dix A Revision History This appendix describes corrections to the MPC563XM Reference Manual For convenience the corrections are grouped by revision A 1 Changes Between Revisions 0 and 1 Table A 1 Changes Between Revisions 0 and 1 Chapter Description Throughout Major reorganization of all content in this document ...

Page 1384: ...fications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use ...

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