Samsung S5PC100, User Manual

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USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0)
8.10 -50
8.2.27 Host Channel-N Characteristics Register (HCCHARn, R/W, Address = 0xEDn*20h)
Channel_number: 0
≤
n
≤
15
HCCHARn Bit Description R/W Reset
Value
ChEna [31] Channel Enable
This field is set by the application and cleared by the OTG host.
•
1'b0 : Disables Channel
•
1'b1 : Enables Channel
R_WS
_SC
1'b0
ChDis [30] Channel Disable
The application sets this bit to stop transmitting/ receiving data
on a channel, even before the transfer for that channel is
complete. The application must wait for the Channel Disabled
interrupt before treating the channel as disabled.
R_WS
_SC
1'b0
OddFrm [29] Odd Frame
This field is set (reset) by the application to indicate that the
OTG host must perform a transfer in an odd (micro) frame. This
field is applicable for only periodic transactions.
•
1'b0 : Even (micro)frame
•
1'b1 : Odd (micro)frame
R/W 1'b0
DevAddr [28:22] Device Address
This field selects the specific device serving as the data source
or sink.
R/W 7'h0
MC/EC [21:20] Multi Count/Error Count
If the Split Enable bit of the Host Channel-n Split Control
register is reset (1’b0), this field indicates to the host the number
of transactions that must be executed per microframe for this
endpoint.
•
2'b00 : Reserved
•
2'b01 : 1 transaction
•
2'b10 : 2 transactions to be issued for this endpoint per
microframe
•
2'b11 : 3 transactions to be issued for this endpoint per
microframe
If HCSPLTn.SpltEna is set, this field indicates the number of
immediate retries to be performed for a periodic split
transactions on transaction errors. This field must be set to at
least 2'b01.
R/W 2'b0
EPType [19:18] Endpoint Type
Indicates the transfer type selected.
•
2'b00 : Control
•
2'b01 : Isochronous
•
2'b10 : Bulk
•
2'b11 : Interrupt
R/W 2'b0
LSpdDev [17] Low-Speed Device
This field is set by the application to indicate that this channel is R/W 1'b0