Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER
5.1-11
2.6 READ DATA CAPTURE
A memory device that receives a read command sends the data to the controller after a read latency (i.e. CAS
latency). After clearing the DQS, the PHY uses the PHY DLL to phase shift the DQS 90 degrees. Using the
shifted DQS, the PHY samples the read data and saves the data into the read data input FIFO, which is located
inside the PHY. Then, the controller fetches the data from the PHY while considering the read latency and the
read fetch delay, and then sends it to the AXI read channel. The following figures show the read data capture
process’s timing diagram for each memory type.
T0 T1 T2 T3 T4 T5 T6
CK
DQS
DQ
SDRAM command
Q0 Q2 Q3
T7
READ
{Q1, Q0} {Q3, Q2}
{Q1, Q0} {Q3, Q2}
PHY read input FIFO
AXI read channel
RL = 3
RL + rd_fetch = 4
T8
90' phase shifted DQS
Q1
negedge
sampling
negedge
sampling
Figure 5.1-5 Timing Diagram of Read Data Capture (DDR2, zero delay, RL=3, rd_fetch=1)
Figure 5.1-5 is for DDR2 having an internal DLL. An internal DLL exists which allows it to send the data after an
exact amount of read latency. If we assume there are minimal or no board/ PHY input delay, if sampling the
negedge (Q1, Q3 sampling), since the data gets saved into the PHY read data input FIFO, the controller sends
the read data to the AXI read channel in ‘read l 1(read fetch)’ cycles. The read fetch cycle is set using the
ConControl.rd_fetch bit-field.
Delay
T0 T1 T2 T3 T4 T5 T6
CK
DQS
DQ
SDRAM command
Q0 Q2 Q3
T7
READ
{Q1, Q0} {Q3, Q2}
{Q1, Q0} {Q3, Q2}
PHY read input FIFO
AXI read channel
RL = 3
RL + rd_fetch = 5
T8
90' phase shifted DQS
Q1
negedge
sampling
negedge
sampling
Figure 5.1-6 Timing Diagram of Read Data Capture (DDR2, non-zero delay, RL=3, rd_fetch=2)
Figure 5.1-6 is different from Figure 5.1-5 because a delay exists. Negedge sampling happens at T5 and T6,
which is one cycle slower than T4/T5 shown in Figure 5.1-4. Therefore, the read fetch cycle should be set to two
since the sampled read data is saved into the read input FIFO slower.