Samsung S5PC100, User Manual

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SD/MMC CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
8.12-76
CONTROL2 Bit Description Reset Value
ENBUSYCH
KTXSTART
[11] CE-ATA I/F mode
Busy state check before Tx Data start state
0 = Disable, 1 = Enable 0
DFCNT [10:9] Debounce Filter Count
Debounce Filter Count setting register for Card Detect signal input
(SDCD#)
00 = No use debounce filter, 01 = 4 iSDCLK,
10 = 16 iSDCLK, 11 = 64 iSDCLK 0
ENCLKOUTH
OLD
[8] SDCLK Hold Enable
Enter and exit of the SDCLK Hold state is done by Host Controller.
0 = Disable, 1 = Enable 0
RWAITMOD
E
[7] Read Wait Release Control
0 = Read Wait state is released by the Host Controller (Auto)
1 = Read Wait state is released by the Host Driver (Manual) 0
DISBUFRD [6] Buffer Read Disable
0 = Normal mode, user can read buffer(FIFO) data using 0x20 register
1 = User cannot read buffer(FIFO) data using 0x20 register. In this
case, the buffer memory is read through memory area (Debug
purpose). 0
SELBASE
CLK
[5:4] Base Clock Source Select
00 or 01 = HCLK, 10 = SCLK_MMC0, SCLK_MMC1, SCLK_MMC2
(from CLKCON), 11 = SCLK_MMC0_48, SCLK_MMC1_48,
SCLK_MMC2_48, (XTI or XEXTCLK) 00
SDINPSIGPC [3] SD Input Signal Power Control Support
If set this field enables input CMD and DAT referencing SD Bus Power
bit in the "PWRCON register".
'0' = No Sync, no switch input enable signal (Command, Data)
'1' = Sync, control input enable signal (Command, Data) 0
- Reserved [2] Reserved 0
ENCLKOUT
MSKCON
[1] SDCLK output clock masking when Card Insert cleared
If this field is High, it is used not to stop SDCLK if No Card state.
'0' = Disable, '1' = Enable 0
HWINITFIN [0] SD Host Controller Hardware Initialization Finish
0 = Not Finish, 1 = Finish 0
NOTES:
1. Ensure to set SDCLK Hold Enable (EnSCHold) if the card does not support Read Wait to guarantee for
Receive data not overwritten to the internal FIFO memory.
2. CMD_wo_DAT issue is prohibited during READ transfer if SDCLK Hold Enable is set.