Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) I
2
C-BUS INTERFACE
8.2-13
3.3 MULTI-MASTER I
2
C-BUS ADDRESS REGISTER
•
I2CADD0, R/W, Address = 0xEC10_0008
•
I2CADD1, R/W, Address = 0xEC20_0008
I2CADD Bit Description Reset Value
Slave address [7:0] 7-bit slave address, latched from the I
2
C-bus.
If serial output enable = 0 in the I2CSTAT, I2CADD is write-
enabled. The I2CADD value is read any time, regardless of the
current serial output enable bit (I2CSTAT) setting.
Slave address : [7:1]
Not mapped : [0]
Undefined
3.4 MULTI-MASTER I
2
C-BUS TRANSMIT/RECEIVE DATA SHIFT REGISTER
•
I2CDS1, R/W, Address = 0xEC10_000C
•
I2CDS1, R/W, Address = 0xEC20_000C
I2CDS Bit Description Reset Value
Data shift [7:0] 8-bit data shift register for I
2
C-bus Tx/Rx operation.
If serial output enable = 1 in the I2CSTAT, I2CDS is write-enabled.
The I2CDS value is read any time, regardless of the current serial
output enable bit (I2CSTAT) setting.
Undefined
3.5 MULTI-MASTER I
2
C-BUS LINE CONTROL REGISTER
•
I2CLC0, R/W, Address = 0xEC10_0014
•
I2CLC1, R/W, Address = 0xEC20_0014
I2CLC Bit Description Reset Value
Filter enable [2] I
2
C-bus filter enable bit.
If SDA port is operating as input, this bit should be High. This filter
prevents from occurred error by a glitch during double of PCLK
time.
0 = Disables Filter
1 = Enables Filter
0
SDA output
delay [1:0] I
2
C-Bus SDA line delay length selection bits.
SDA line is delayed as following clock time(PCLK)
00 = 0 clocks 01 = 5 clocks
10 = 10 clocks 11 = 15 clocks
00