Samsung S5PC100, User Manual

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CCAN S5PC100 USER’S MANUAL (REV1.0)
8. 5-20
6.2.5 Interrupt Register
•
CAN0_INTR, R/W, Address = 0xEC70_0010
•
CAN1_INTR, R/W, Address = 0xEC80_0010
CANn_INTR Bit Description R/W Reset
Value
IntID15-0 [15:0] Interrupt Identifier (the number here indicates the source of the
interrupt)
0x0000: No interrupt is pending
0x0001-0x0020: Number of Message Object which caused the
interrupt
0x0021-0x7FFF: unused
0x8000: Status Interrupt
0x8001-0xFFFF: unused
R 0
6.2.6 Test Register
•
CAN0_TEST, R/W, Address = 0xEC70_0014
•
CAN1_TEST, R/W, Address = 0xEC80_0014
CANn_TEST Bit Description R/W Reset
Value
Reserved [15:8] Reserved R 0
Rx [7] Monitors the actual value of the CAN_RX Pin
1 = The CAN bus is recessive (CAN_RX = '1')
0 = The CAN bus is dominant (CAN_RX = '0') R 0
Tx1-0 [6:5] Control of CAN_TX Pin
00 = Reset value, CAN_TX is controlled by the CAN Core
01 = Sample Point is monitored at CAN_TX pin
10 = CAN_TX pin drives a dominant ('0') value
11 = CAN_TX pin drives a recessive ('1') value
R/W 0
LBack [4] Loop Back Mode
1 = Enables Loop Back Mode
0 = Disables Loop Back Mode
R/W 0
Silent [3] Silent Mode
1 = The module is in Silent Mode
0 = Normal operation
R/W 0
Basic [2] Basic Mode
1 = IF2 Registers used as Tx Buffer, IF2 Registers used as Rx
Buffer
0 = Basic Mode disabled
R/W 0
Reserved [1:0] Reserved R 0
NOTE : Write access to the Test Register is enabled by setting bit Test in the CAN Control Register. The different test
functions may be combined, but Tx1-0
≠
“00” disturbs message transfer.