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Power Management
S5PC100 USER’S MANUAL (REV1.0)
2.4-22
6.1 SRAM
SRAM in Top domain has four power modes: Run, Stand-by, Retention, and Power-down mode.
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In Run mode, read and write access to SRAM are performed normally.
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In Stand-by mode, SRAM chip select is deactivated, so that there is no read and write access.
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In Retention mode, power is provided to only core of SRAM, and power to peripheral circuitry is off internally.
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In Power-down mode, all power to core and peripheral circuitry is off.
The list of SRAM in Top domain is as follows: CCAN, IRDA, MODEM IF, USB_OTG, SDMMC, CSSYS, SECSS,
internal RAM 0, 1, and 2. (Refer to STOP_MEM_CFG register in Section 10 REGISTER DESCRIPTION)
In NORMAL mode, run, or stand-by mode is used.
Run mode is used if there is read and write access, while stand-by mode is used if there is no read and write
access. The change between these two modes is done by corresponding SRAM control logic.
In IDLE mode, and DEEP-IDLE mode (top domain on), SRAM keeps its operation or power state in NORMAL.
In DEEP-IDLE mode (top domain is off), SRAM in TOP module enters stand-by, retention, or power-down mode.
Before entry to this mode, you must set the TOP_MEMORY_ON_DIDLE and TOP_MEMORY_RET_ON_DIDLE
field PWR_CFG in PMU.
In STOP mode and DEEP-STOP mode, stand-by, retention, and power-down mode can be entered.
Before entry to STOP mode, you must set the TOP_MEMORY_ON and TOP_MEMORY_RET field of STOP_CFG
register in PMU to determine which power mode SRAM enters during STOP mode. And each SRAM can be
separately set in STOP_MEM_CFG register.
In SLEEP mode, power to SRAM is off, so the data in SRAM is lost. Power mode of SRAM in SLEEP mode has
no meaning.
6.2 ROM
ROM has two power modes: Run, and Stand-by mode.
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In Run mode, read access to ROM is performed normally.
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In Stand-by mode, chip selection to ROM is deactivated, so that there is no read access.
In NORMAL mode, both power modes are used. Run mode is used if there is read access, while Standby-mode is
used if there is no read access. The change between these two modes is done by ROM control logic.
In IDLE mode and DEEP-IDLE mode (top domain on), ROM keeps its operation or power state in NORMAL.
To enter DEEP-IDLE mode (top domain is off), STOP mode and DEEP-STOP mode, s/w should not access ROM
so that ROM enter Stand-by mode.
In SLEEP mode, power to ROM is off. Power mode of ROM in SLEEP mode has no meaning.
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...