Samsung S5PC100, User Manual, Page: 164 / 1863

CLOCK CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
2.3-14
7.3 SPECIAL CLOCK TABLE
The Table 2.3-7 summarizes special clocks in S5PC100.
Table 2.3-7 Special Clock in S5PC100
Name Description Input range Source
SCLK_ONENAND,
SCLK_ONENAND_2 OneNAND controller
operation clock ~88MHz (ONENAND_2)
~166MHz (ONENAND)
(A, M)PLL
SCLK_IRDA IrDA operation clock
48MHz fix
(+-960Hz margin)
(E,M,H)PLL, USB_48
SCLK_TVENC SD-video pixel clock 54MHz fix Clock doubler (27MHz x2)
SCLK_VDAC SD-video pixel clock 54MHz fix Clock doubler (27MHz x2)
SCLK_LCD DISPLAY clock ~133MHz (E,M,H)PLL, VCLK_54
SCLK_FIMC0, 1, 2 POST function clock ~133MHz (E,M,H)PLL, VCLK_54
SCLK_HDMI HD-video pixel clock
27MHz, 74.176MHz,
74.25MHz fix
PAD_27, HPLL
SCLK_AUDIO0
I2S0, PCM0-operation
reference clock 2.048MHz ~
73.7280MHz
CPAD, (E,M,H)PLL, Audio PAD
SCLK_AUDIO1
I2S1, PCM1-operation
reference clock
Same as above Same as above
SCLK_AUDIO2 I2S2-operation clock Same as above Same as above
SCLK_SPDIF SPDIF-operation clock Same as above SCLK_AUDIO(0,1,2)
SCLK_SPIx
SCLK_SPIx_48 SPI-operation reference
clock ~50MHz (100MHz/2)
(SPI divides input clock.)
CPAD, (E,M,H)PLL
(SCLK_SPIx) /
USB_48 (SCLK_SPIx_48)
Uart_eclk
SCLK_UART UART-operation
reference clock
~133MHz
From UART PAD /
(E,M,H)PLL (SCLK_UART)
SCLK_MMC(0,1)
SCLK_MMC(0,1)_48
SDMMC-operation
reference clock
~52MHz
(E,M,H)PLL, C_PAD /
USB_48 (SCLK_MMCX_48)
SCLK_UHOST1.1
USB HOST-operation
reference clock
48MHz
(E,M,H)PLL, USB_48 (OTG
PHY)
SCLK_UOTG
USB OTG-operation
reference clock
30MHz USB_48 (OTG PHY)
CAM_PCLK /
SCLK_LCD
FIMC-operation clocks
(Pixel clock from CIS/
Shared clock with LCD)
~83MHz (CAM_PCLK)
~133MHz (SCLK_LCD)
Direct from CAM clock PAD
(CAM_PCLK) /
Clock controller (SCLK_LCD)
SCLK_CAM Clock to CAM ~83MHz (A, M)PLL
SCLK_MIPI_PHY Clock for MIPI D-PHY 27MHz PAD_27
ac_bit_clk
AC97 codec clock
(ext chip generates)
12.288MHz fix
Direct from AC97 clock PAD to
AC97 IP
pwm_eclk Auxiliary clock ~70MHz
Direct from PWM clock PAD to
PWM IP