Samsung S5PC100, User Manual, Page: 875 / 1863

USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0)
8.10 -32
GINTSTS Bit Description R/W Reset
Value
IEPInt [18] IN Endpoints Interrupt
The core sets this bit to indicate that an interrupt is pending on
one of the IN endpoints of the core (in Device mode). The
application must read the Device All Endpoints Interrupt (DAINT)
register to determine the exact number of the IN endpoint on
which the interrupt occurred, and then read the corresponding
Device IN Endpoint-n Interrupt (DIEPINTn) register to determine
the exact cause of the interrupt. The application must clear the
appropriate status bit in the corresponding DIEPINTn register to
clear this bit. R 1'b0
EPMis [17] Endpoint Mismatch Interrupt
Indicates that an IN token has been received for a non-periodic
endpoint, but the data for another endpoint is present in the top
of the Non-Periodic Transmit FIFO and the IN endpoint mismatch
count programmed by the application has expired.
R_SS
_WC
1’b0
Reserved [16] - 1'b0
EOPF [15] End of Periodic Frame Interrupt
Indicates that the period specified in the Periodic Frame Interval
field of the Device Configuration register (DCFG.PerFrInt) has
been reached in the current microframe.
R_SS
_WC
1'b0
ISOutDrop [14] Isochronous OUT Packet Dropped Interrupt
The core sets this bit if it fails to write an isochronous OUT packet
into the RxFIFO because the RxFIFO does not have enough
space to accommodate a maximum packet size packet for the
isochronous OUT endpoint.
R_SS
_WC
1'b0
EnumDone [13] Enumeration Done
The core sets this bit to indicate that speed enumeration is
complete. The application must read the Device Status (DSTS)
register to obtain the enumerated speed. R_SS
_WC
1'b0
USBRst [12] USB Reset
The core sets this bit to indicate that a reset is detected on the
USB. R_SS
_WC
1'b1
USBSusp [11] USB Suspend
The core sets this bit to indicate that a suspend was detected on
the USB. The core enters the Suspended state if there is no
activity on the line_state signal for an extended period of time. R_SS
_WC
1'b0
ErlySusp [10] Early Suspend
The core sets this bit to indicate that an Idle state has been
detected on the USB for 3 ms. R_SS
_WC
1'b0
Reserved [9] - 1'b0
Reserved [8] - 1'b0