Samsung S5PC100, User Manual, Page: 1402 / 1863

S5PC100 USER’S MANUAL (REV1.0) TVOUT & VIDEO DAC
9.7-81
7.6
FUNCTIONAL DESCRIPTION
This is a 10-bit 54MSPS digital-to-analog data converter and uses segment architecture for 6bits of MSB,
binaryweighted architecture for 4-bits of LSB. It consist of 1
st
latch block, decoder block, 2
nd
latch block, amp
block, Current Mirror (CM) block and current cell matrix block. This IP uses reference current to decide the 1LSB
current size by dividing the reference current by 31 times. Therefore the reference current must be constant by
using high DC gain amp block. The most significant block of this IP is current cell matrix and it must maintain the
uniformity at each analog current cell, therefore layout designer must take care of the matching characteristics of
analog current cell matrix and CM block. More than 90% of supply current is dissipated at current cell matrix block
and AMP block. It uses SEC standard cell as all digital cell of latch, decoder and buffer. To adjust full scale output
current, the “R
SET
” resistor value (connected to IREF pin) must be decided. Its voltage output is obtained by
connecting R
LOAD
aganst GND (connected to IOUT pin)
7.6.1 Integral Non Linearity (or ILE):
INL is the maximum deviation of the input/ output characteristic from a straight line passed through its end points.
The difference between the ideal and actual characteristics is called the INL profile.
7.6.2 Differential Non Linearity (or DLE):
DNL is the maximum deviation in the output step size from the ideal value of one least significant bit.
7.6.3 Monotonicity:
A D/A converter is monotonic if the output either increases or remains constants as the digital input increases.
7.6.4 Offset Error:
The deviation of the output current from the ideal of zero is called offset error. For IO, 0mV output expected if the
inputs are all 0s.
7.6.5 Gain Error:
The difference between the actual and ideal output span. The actual span is determined by the output if all inputs
are set to 1s minus the output if all inputs are set to 0s.
7.6.6 Output Compliance Range:
The range of allowable voltage at the output of a current-steering DAC. Operation beyond the maximum
compliance limits causes either output stage saturation or breakdown resulting in nonlinear performance.
7.6.7 Full scale output current
The full scale output current I
FS
is set by the reference voltage V
VREF
and the external resistor R
SET
. This is
expressed as:
I
FS
=V
VREF
×
1023/(R
SET
×
31)
7.6.8 Full scale output voltage control
The full scale output voltage V
FS
is set by full scale output current I
FS
and the external resistor R
LOAD
. This is
expressed as:
VFS=I
FS
×
R
LOAD
FS [2:0] are the control bits to vary V
FS
, [000] being default as shown in the following table. This is used for small
adjustment in V
FS
.