Samsung S5PC100, User Manual

Page: 569 / 1863

S5PC100 USER’S MANUAL (REV1.0) DMA CONTROLLER
6.1-21
3.2.7 Configuration Register4 for DMA_PERI(0,1) (CR4, R)
•
CR4 for DMA_PERI0, R, Address = 0xE900_0E10
•
CR4 for DMA_PERI1, R, Address = 0xE920_0E10
CR4 Bit Description Reset Value
PNS [31:0]
Provides the security state of the peripheral request interfaces:
Bit [ N ] = 1 Assigns peripheral request interface N to the Non-
secure state.
32’hffff_ffff
0xFFFF_FFFF
3.2.8 Configuration Register DN for DMA_PERI(0,1) (CRdn, R)
•
CRDn for DMA_PERI0, R, Address = 0xE900_0E14
•
CRDn for DMA_PERI1, R, Address = 0xE920_0E14
CRDn Bit Description Reset Value
data_buffer_dep [29:20]
The number of lines that the data buffer contains
b000000111 = 8 lines
0x7
rd_q_dep [19:16]
The depth of the read queue
b0111 = 8 lines
0x7
rd_cap [14:12]
Read issuing capability that programs the number of
outstanding read transactions
b011 = 4
0x3
wr_q_dep [11:8]
The depth of the write queue
b0111 =8 lines
0x7
wr_cap [6:4]
Write issuing capability that programs the number of
outstanding write transactions
b011 = 4
0x3
data_width [2:0]
The data bus width of the AXI interface
b010 = 32-bit
0x2