Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) MIPI DSIM
8.7-17
3.2 DETAILED DECRIPTION
3.2.1 Status Register (DSIM_STATUS, R, Address = 0xECB0_0000)
This registers reads and checks status Internal & interface status.
FSM status, Line buffer status, current image line number, etc.
DSIM_STATUS Bit Description R/W Reset Value
PllStable [31] D-phy pll generates stable byteclk. R 0
Reserved [30:21] Reserved - 0
SwRstRls [20] Software reset status
0 = Reset state
1 = Release state
R 0
Reserved [19:17] Reserved - 0
Direction [16] Data direction indicator
0 = Forward direction
1 = Backward direction
R 1
Reserved [15:11] Reserved - 0
TxReadyHsClk [10] HS clock ready at Clock lane
0 = Not ready for transmitting HS data at clock lane.
1 = Ready for transmitting HS data at clock lane.
R 0
UlpsClk [9] ULPS indicator at clock lane
0 = No ULPS in clock lane
1 = ULSP in clock lane
R 1
StopstateClk [8] Stop state indicator at clock lane
0 = No Stop state in clock lane
1 = Stop state in clock lane
R 0
UlpsDat[3:0] [7:4] ULPS indicator at data lanes
UlpsDat[0] : Data lane 0
UlpsDat[1] : Data lane 1
UlpsDat[2] : Data lane 2
0 = No ULPS in each data lane.
1 = ULPS in each data lane.
R F
StopstateDat[3:0] [3:0] Stop state indicator at data lane
StopstateDat[0] : Data lane 0
StopstateDat[1] : Data lane 1
StopstateDat[2] : Data lane 2
0 = No Stop state in each data lane
1 = Stop state in each data lane
R 0