S5PC100 USER’S MANUAL (REV1.0)
USB HOST CONTROLLER
8.9-11
Table 8.9-2 UHCCON Bit Definitions
UHCCON
Bit
Description
R/W
Reset Value
Reserved
[31:11]
Reserved
-
RWE [10]
RemoteWakeupEnable
The host controller driver uses this bit to enable or disable
the remote wakeup feature upon the detection of upstream
resume signaling. If this bit is set and the ResumeDetected
bit in HcInterruptStatus (Refer to Section 20.8.4) is set, a
remote wake-up is signaled to the host system. Setting this
bit has no impact on the generation of hardware interrupt.
0 = Disable remote wake-up is signaling to the host system.
1 = Enable remote wake-up is signaling to the host system.
R/W
RWC [9]
RemoteWakeupConnected
This bit indicates whether the UHC supports remote wake-
up signaling. If remote wake-up is supported and used by
the system, it is the responsibility of system firmware to set
this bit after reset. The UHC clears the bit upon a hardware
reset, but does not alter it upon a software reset
0 = UHC does not support remote wake-up signaling.
1 = UHC supports remote wake-up signaling.
R/W
IR [8]
InterruptRouting
This bit determines the routing of interrupts generated by
events registered in the UHC Interrupt Status register,
UHCINTS (Refer to Section 20.8.4). If clear, all interrupts are
routed to the normal host bus-interrupt mechanism. If set,
interrupts are routed to the system management interrupt
(SMI). The host controller driver clears this bit on a hardware
reset, but it does not alter this bit on a software reset. The
host controller driver uses this bit as a tag to indicate the
ownership of UHC. This implementation of the OHCI host
controller does not support SMI. Therefore, the host
controller driver must never set this bit.
0 = All interrupts are routed to the normal host bus interrupt
mechanism.
1 = Interrupts are routed to the SMI.
R/W
HCFS [7:6]
HostControllerFunctionalState
This field of two bits displays the current functional state of
the USB host controller.
0b00 = USBRESET 0b01 = USBRESUME
0b10 = USBOPERATIONAL 0b11 =
USBSUSPEND
A transition to USBOPERATIONAL from another state
causes an SOF generation to begin 1 ms later. The host
controller driver determines whether UHC has started
sending SOFs by reading the StartofFrame field of
HcInterruptStatus (Refer to Section 20.8.4).
This field is changed by UHC if in the USBSUSPEND state.
UHC moves from the USBSUSPEND state to the
USBRESUME state after detecting the resume signaling
from a downstream port.
R/W
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...