Samsung S5PC100, User Manual

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USB HOST CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
8.9-40
5.2.23 USB HcRhPortStatus 2 Register (UHCRHPSTAT2, Address = 0xED40_0058)
The UHC Root Hub Port Status[2:1] registers control and report USB ports 1 and 2 events on a per-port basis.
The lower word of UHCRHPS1/2 reflects the port status, whereas the upper word reflects the status change bits.
Some status bits are implemented with special write behavior (see Table 8.9-23). If a transaction (token through
handshake) is in progress when a write to change port status occurs, the resulting port-status change must be
postponed until the transaction completes. The register organization and individual bit definitions are shown in
Table 8.9-23.
Table 8.9-23 UHCRHPSTAT2 Bit Definitions
UHCRHPSTAT2 Bit Description R/W Reset Value
Reserved [31:21] Read as unknown and must be written as zero. -
PRSC [20] PortResetStatusChange
This bit is set at the end of the 10-ms port reset signal.
A 1 indicates that the port reset is complete. A 0
indicates that the port reset is not yet complete. The
HCD writes a 1 to clear this bit. Writing a 0 has no
effect.
0 = Port reset is not complete.
1 = Port reset is complete. R/W
POCIC [19] PortOverCurrentIndicatorChange
This bit is valid only if over-current conditions are
reported on a per-port basis. This bit is set if root hub
changes the port over-current indicator bit. The HCD
writes a 1 to clear this bit. Writing a 0 has no effect
0 = No change in PortOverCurrentIndicator.
1 = PortOverCurrentIndicator has changed. R/W
PSSC [18] PortSuspendStatusChange
This bit is set by the UHC if the full resume sequence
has been
complete. This sequence includes the 20-ms resume
pulse, LS EOP, and 3-ms re-synchronization delay. The
HCD writes a 1 to clear this bit. Writing a 0 has no
effect. This bit is also cleared if PortResetStatusChange
is set.
0 = Resume is not complete.
1 = Resume complete. R/W
PESC [17] PortEnableStatusChange
This bit is set if events (such as over-current condition,
disconnect, switched-off power, or operational bus R/W