Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) IROM CODE
2.6-3
down modes. Because the system is entered into ESLEEP mode on the emergency case such as battery fault,
there is no safe memory space on the whole system. So, any status information will not be saved to DRAM before
entering ESLEEP mode.
Finally, the restoring pervious state function is required on wake up from SLEEP, wake up from DEEP_STOP,
and wake up from DEEP_IDLE.
2.2 FUNCTIONAL SEQUENCE
Full booting sequence in BL0 is as follows,
1. Initialize the PLL & Clock setting with fixed value
2. Initialize the stack and heap region.
3. Initialize the Instruction Cache controller.
4. Load BL1 from the booting device to iRAM.
*
5. If secure booting is enabled, execute integrity check.
6. If integrity check passes, then jump to 0x34010.(First 4word is reserved)
7. If integrity check fails, then it stops.
*
NOTE1. In case of SD/MMC, iROM code load 9KB at 0x34000 from end of memory device.
*
NOTE2. In case of OneNAND and NAND, iROM code load 16KB at 0x34000 from the beginning(Block 0) of
memory device block.
*
NOTE3. Bad Block Information is in 6th byte of Spare Area(Block#0) in case of 512 byte Page NAND device.
And the rest of NAND device(2KB page size) has Bad Block Information in the first byte of Spare Area.
2.3 CLOCK SETTING
The setting values for PLL’s and clock dividers are as follows.
•
APLL: M=400, P=4, S=1
•
MPLL: M=106, P=4, S=2
•
EPLL: M=110, P=4,S=4
•
DIV
APLL
= 1 (1/2 divider)
•
DIV
ARM
= 0 (1/1 divider)
•
DIV
D0_BUS
= 2 (1/3 divider)
•
DIV
D1_BUS
= 0 (1/1 divider)
•
DIV
MPLL
= 0 (1/1 divider)
•
DIV
MPLL2
= 0 (1/1 divider)
Table 2.6-2 shows the clock frequencies after the initialization of the PLL’s in BL0.
Table 2.6-2 BL0’s Clock Speed
X-tal(MHz) ARM Clock (MHz) HCLK_D0(MHz) HCLK_D1(MHz) EPLL Clock (MHz)