Samsung S5PC100, User Manual

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I2S CONTROLLER(5.1CH) S5PC100 USER’S MANUAL (REV1.0)
10.2-24
8.8 I2S INTERFACE TRANSMIT DATA REGISTER FOR TXFIFO_S (I2STXDS, W, ADDRESS = 0XF200_001C)
I2STXDS Bit Description R/W Reset
Value
I2STXDS [31:0] Secondary TX FIFO_S write data. Note: The left/ right
channel data is allocated as the following bit fields.
R[31:16], L[15:0] if 16-bit BLC
R[23:16], L[7:0] if 8-bit BLC
Refer to Figure 10.2-7 if 24-bit BLC
W 0x00
8.9 I2S AHB DMA CONTROL REGISTER (I2SAHB, R/W, ADDRESS = 0XF200_0020)
I2SAHB Bit Description R/W Reset
Value
Reserved [31:28] Reserved R 0x00
I2SLVL3EN [27] Enable buffer level 3 interrupt.
0 = Disables I2SLVL3INT.
1 = Enables I2SLVL3INT.
R/W 0
I2SLVL2EN [26] Enable buffer level 2 interrupt.
0 = Disables I2SLVL2INT.
1 = Enables I2SLVL2INT.
R/W 0
I2SLVL1EN [25] Enable buffer level 1 interrupt.
0 = Disables I2SLVL1INT.
1 = Enables I2SLVL1INT.
R/W 0
I2SLVL0EN [24] Enable buffer level 0 interrupt.
0 = Disables I2SLVL0INT.
1 = Enables I2SLVL0INT.
R/W 0
I2SLVL3INT [23] Buffer level 3 interrupt status flag.
During DMA operation, if generated address in DMA matches
with I2SLVL3ADDR, this flag is set. To clear this flag, use
I2SLVL3CLR field.
R 0
I2SLVL2INT [22] Buffer level 2 interrupt status flag.
During DMA operation, if generated address in DMA matches
with I2SLVL2ADDR, this flag is set. To clear this flag, use
I2SLVL2CLR field.
R 0
I2SLVL1INT [21] Buffer level 1 interrupt status flag.
During DMA operation, if generated address in DMA matches
with I2SLVL1ADDR, this flag is set. To clear this flag, use
I2SLVL1CLR field.
R 0
I2SLVL0INT [20] Buffer level 0 interrupt status flag.
During DMA operation, if generated address in DMA matches
with I2SLVL0ADDR, this flag is set. To clear this flag, use
I2SLVL0CLR field.
R 0