Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) CRYPTO ENGINE BLOCK
11.3-17
4.2 DMA AND INTERRUPT CONFIGURATION REGISTER
4.2.1 DMA and Interrupt Configuration Control/Status Register. (DnI_Cfg, R/W, Address = 0xF400_0000)
DnI_Cfg Bit Description Reset Value
WrPrivMismatch [31]
SFR Write Access Privilege Mismatch Status bit. If set to '1',
SFR Write Access Privilege Mismatch occurs.
1’b0
RdPrivMismatch [30]
SFR Read Access Privilege Mismatch Status bit. If set to '1',
SFR Read Access Privilege Mismatch occurs.
1’b0
Reserved [29:23] Reserved
SHA_intr_Status [22] SHA-1/PRNG interrupt status (Resets to 0 if read). 1’b0
DES_intr_Status [21] DES/TDES interrupt status (Resets to 0 if read). 1’b0
AES_intr_Status [20] AES interrupt status (Resets to 0 if read). 1’b0
Reserved [19:18] Reserved
FTx_intr_Status [17] FIFO-Tx interrupt status (Resets to 0 if read). 1’b0
FRx_intr_Status [16] FIFO-Rx interrupt status (Resets to 0 if read). 1’b0
Reserved [15] Reserved
SHA_intr_En [14] SHA-1/PRNG interrupt enabled 1’b0
DES_intr_En [13] DES/TDES interrupt enabled 1’b0
AES_intr_En [12] AES interrupt enabled 1’b0
Reserved [11:10] Reserved
FTx_intr_En [9] FIFO-Tx interrupt enabled 1’b0
FRx_intr_En [8] FIFO-Rx interrupt enabled 1’b0
Reserved [7] Reserved
TxTrgLevel [6:5] Tx side DMA trigger level setting.
00 = 8-word
01 = 16-word
10 = 24-word
11 = Reserved
2’b00
TxDmaEnb [4] Tx side DMA enable bit (1= Enable) 1’b0
Reserved [3] Reserved
RxTrgLevel [2:1]
Rx side DMA trigger level setting.
00 = 8-word
01 = 16-word
10 = 24-word
11 = Reserved
2’b00
RxDmaEnb [0] Rx side DMA enable bit (1= Enable) 1’b0
Note: 1. The SHA-1 related modules(HMAC, SHA-1, and PRNG) do not support 24-word trigger level setting
(DnI_Cfg[2:1], DnI_Cfg[6:5]).
2. The SECSS interrupt must be masked in case of SECSS DMA mode operation.
3. The SECSS does not recommend SECSS interrupt mode instead of polling mode in case of SECSS
FiFo mode operation.