Samsung S5PC100, User Manual, Page: 39 / 1863

S5PC100 USER’S MANUAL (REV1.0) BALL MAP & SIZE (SingleChip)
1.1-3
Table 1.3-2 S5PC100 521 FCFBGA Pin Assignment
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Pin Number Order (2/4)
Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name
J8 Xm0FCLE L12 VSS N9 XciRESET R17 VDD_INT
J9 Xm0FWEn L13 VSS N11 Xm0ADDR[3] R19 XEINT[7]
J10 Xm0FREn L14 VSS N12 VDD_INT R20 XEINT[6]
J11 VDDQ_DDR L15 VSS N16 VSS R21 Xmmc0DATA[7]
J12 Xm0OEn L16 VDD_ARM N17 VDDQ_EXT R24 Xmmc1CDn
J13 Xm0WAITn L17 VDD_ARM N19 XjTMS R25 Xmmc1DATA[1]
J14 Xm0IORDn L19 Xmmc0CLK N20 XspiMISO[1] R26 VDDQ_EXT
J15 VSS L20 XspiCSn[1] N21 Xmmc0DATA[2] R27 XDDR2SEL
J16 VDD_ARM L21 XjTDO N24 Xmmc0DATA[0] T1 XciDATA[4]
J17 VDD_ARM L24 XpwmTOUT[2] N25 Xmmc1CMD T2 XciFIELD
J18 VDD_ARM L25 XuCTSn[1] N26 XjTRSTn T3 XvVDEN
J19 VDD_ARM L26 Xi2c0SDA N27 Xmmc0CDn T4 XvVCLK
J20 VSS L27 XspiCLK[1] P1 XvVD[15] T7 XiemSPWI
J21 VDD_ARM M1 XvVD[1] P2 XvVD[9] T8 XciVSYNC
J24 XuTXD[1] M2 XvVD[10] P3 XvVD[8] T9 XusbDRVVBUS
J25 XuTXD[3] M3 XvVD[2] P4 XvVD[4] T11 XvVD[0]
J26 XuCLK M4 Xm0CSn[5] P7 XvVD[13] T12 VDDQ_MMC
J27 XspiCSn[0] M7 XvVD[17] P8 XciDATA[0] T13 VSS
K1 XvVD[21] M8 XvVD[12] P9 VDDQ_LCD T14 VSS
K2 Xm0ADDR[6] M9 XvVD[20] P11 XvVD[16] T15 VSS
K3 VDDQ_M0 M11 VDD_INT P12 XvVD[11] T16 VSS
K4 VSS M12 VDD_INT P16 VSS T17 VDD_INT
K7 Xm0ADDR[7] M13 VDD_INT P17 VDD_INT T19 XEINT[24]
K8 Xm0ADDR[17] M14 VDD_INT P19 XjTCK T20 XnRESET
K9 Xm0ADDR[19] M15 VDD_INT P20 XEINT[16] T21 XEINT[5]
K19 VDD_ARM M16 VSS P21 Xmmc0DATA[1] T24 XEINT[3]
K20 VSS M17 VDD_ARM P24 Xmmc1DATA[3] T25 XEINT[22]
K21 Xmmc0DATA[5] M19 Xmmc0DATA[4] P25 Xmmc1DATA[0] T26 VSS
K24 Xi2c1SCL M20 Xmmc0DATA[3] P26 Xmmc1CLK T27 XjTDI
K25 XuCTSn[0] M21 XspiMOSI[1] P27 Xmmc1DATA[2] U1 XciDATA[2]
K26 Xi2c1SDA M24 XspiMOSI[0] R1 XvVD[3] U2 VDDQ_CI
K27 XspiCLK[0] M25 XspiMISO[0] R2 XvVSYNC U3 XciPCLK
L1 XvVD[7] M26 Xmmc0DATA[6] R3 XvHSYNC U4 XciCLKenb
L2 XvVD[14] M27 Xmmc0CMD R4 XciDATA[5] U7 Xi2s0LRCK
L3 Xm0CSn[1] N1 Xm0CSn[4] R7 Xi2s0SDO[0] U8 Xi2s1SDO
L4 Xm0CSn[0] N2 XvVD[23] R8 XciHREF U9 XciDATA[7]
L7 Xm0ADDR[8] N3 XvVD[22] R9 VDD_INT U11 XmsmADDR[9]
L8 Xm0ADDR[15] N4 VDDQ_LCD R11 XciDATA[6] U12 Xi2s0SDI
L9 Xm0ADDR[14] N7 XvVD[18] R12 XvVD[5] U13 XvVD[19]
L11 VSS N8 XvVD[6] R16 VSS U14 Xmmc2DATA[3]