Samsung S5PC100, User Manual

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USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0)
8.10 -28
8.2.9 Core Reset Register (GRSTCTL, R/W, Address = 0xED20_0010)
The application uses this register to reset various hardware features inside the core.
GRSTCTL Bit Description R/W Reset
Value
AHBIdle [31] AHB Master Idle
Indicates that the AHB Master State Machine is in the IDLE
condition. R 1'b1
DMAReq [30] DMA Request Signal
Indicates that the DMA request is in progress. Used for debug. R 1'b0
Reserved [29:11] - 19'h0
TxFNum [10:6] TxFIFO Number
This is the FIFO number. Use TxFIFO Flush bit to flush FIFO
number. This field must not be changed until the core clears the
TxFIFO Flush bit.
•
5'h0 : Non-Periodic TxFIFO flush
•
5'h1 : Periodic TxFIFO 1 flush in Device mode for
Periodic TxFIFO flush in Host mode
•
5'h2 : Periodic TxFIFO 2 flush in Device mode
• • •
•
5'hF : Periodic TxFIFO 15 flush in Device mode
•
5'h10 : Flush all the Periodic and Non-Periodic TxFIFOs in the
core
R/W 5'h0
TxFFlsh [5] TxFIFO Flush
This bit selectively flushes a single or all transmit FIFOs, but
cannot flush if the core is in the middle of a transaction. The
application must only write this bit after checking that the core is
neither writing to the TxFIFO nor reading from the TxFIFO. The
application must wait until the core clears this bit before
performing any operations. This bit takes 8 clocks to clear.
R_WS
_SC
1'b0
RxFFlsh [4] RxFIFO Flush
The application flushes the entire RxFIFO using this bit, but must
first ensure that the core is not in the middle of a transaction. The
application must only write to this bit after checking that the core
is neither reading from the RxFIFO nor writing to the RxFIFO.
The application must wait until the bit is cleared before
performing any other operations. This bit takes 8 clocks to clear. R_WS
_SC
1'b0
INTknQFlsh [3] IN Token Sequence Learning Queue Flush
The application writes this bit to flush the IN Token Sequence
Learning Queue. R_WS
_SC
1'b0
FrmCntrRst [2] Host Frame Counter Reset
The application writes this bit to reset the (micro) frame number
counter inside the core. If the (micro) frame counter is reset, the
subsequent SOF sent out by the core will have a (micro) frame
number of 0. R_WS
_SC
1'b0