Samsung S5PC100, User Manual

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3D-ACCELERATOR S5PC100 USER’S MANUAL (REV1.0)
9.6-64
7.1.6 Special Function Register For Hw Configuration (FGPS) (PS_EXEMODE, R/W, ADDRESS =
0X0004_C800)
PS_ExeMode Bit Description Reset Value
Reserved [31:1] Reserved 0
PS_ExeMode [0] Select Pixel Shader Execution Mode Register
0 = HOST Access Mode (PSHostMode). HOST CPU can access
HW configuration register. Some program register such as
instruction memory, float/integer/bool constant register cab be
downloaded in this mode.
1 = Pixel Shader Execution Mode. (PSExeMode). Pixel shader
runs normal operation. In this mode, host CPU can read only the
status register of PS_IBStatus and PS_IsNotEmpty. If host CPU
change the other registers value, the pixel shader operation is
unpredictable.
The mode change constraints.
PSHostMode
Æ
PSExeMode :
Set All configuration register value
Load Instruction, Constant F/B/I register
Confirm PS_IBStatus is ‘0’.
Assert PS_ExeMode to ‘1’.
PSExeMode
Æ
PSHostMode :
Confirm IsNotEmpty_PS is ‘0’ for all pixel shader.
Assert PS_ExeMode to ‘0’
0b
7.1.7 Special Function Register For Hw Configuration (FGPS) (PS_ PCSTART, R/W, ADDRESS =
0X0004_C804)
PS_PCStart Bit Description Reset Value
Reserved [31:9] Reserved 0
PS_PCStart [8:0] When the pixel shader start operation, the first instruction, which
is stored at PS_PCStart, is fetched from instruction memory.
This register value should be copied to pixel shader program
counter by PS_PCCopy register before shader starts.This value
is the address of first instruction which is executed when the
pixel shader starts. It is copied to program counter of pixel
shader by command.
0x0