Samsung S5PC100, User Manual

Page: 695 / 1863

IRDA S5PC100 USER’S MANUAL (REV1.0)
8.4-16
6.7 IRDA FIFO CONTROL REGISTER(IRDA_FCR, R/W, ADDRESS = 0XEC60_0018)
IrDA _FCR Bit Description Initial State
Rx FIFO Trigger
Level Select [7:6] Receiver FIFO trigger level selection.
Bit 7 Bit 6 64-byte RX FIFO
0 0 01
0 1 16
1 0 32
1 1 56
00
FIFO Size Select [5] Must set to '1', to use 64 bytes TX and RX FIFO. 0
TX FIFO Clear
Notification [4] This bit will be activated if the FIFO clear is over. This bit is cleared
by the CPU reads this register. 0
RX FIFO CLEAR
NOTIFICATION [3] This bit will be activated if the FIFO clear is over. This bit is cleared
by the CPU reads this register. 0
Tx FIFO Reset [2] TX FIFO reset. If set to '1', bit 2 clears all bytes in the transmitter
FIFO and reset its counter to '0'. A '1' written to bit 2 is self-clearing. 0
Rx FIFO Reset [1] RX FIFO reset. If set to '1', bit 1 clears all bytes in the receiver FIFO
and reset its counter to '0'. A '1' written to bit 1 is self clearing. 0
FIFO Enable [0] FIFO enable. If set to '1', bit 0 enables both the transmitter and
receiver FIFOs. Bit 0 must be a '1' when setting other IrDA_FCR
bits. Changing bit 0 clears the FIFO. 0