Samsung S5PC100, User Manual

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I2S CONTROLLER(2CH) S5PC100 USER’S MANUAL (REV1.0)
10.3-16
8.2.2 I2S Interface Mode Register (I2SMOD, R/W, Address = 0XF210_0004, 0XF220_0004)
y
I2SMOD1, R/W, Address = 0XF210_0004
y
I2SMOD2, R/W, Address = 0XF220_0004
I2SMOD Bit Description R/W Reset
Value
Reserved [31:15] Reserved R/W
BLC [14:13] Bit Length Control Bit Which decides transmission of
8/16/24 bits per audio channel
00 = 16 Bits per channel
01 = 8 Bits per Channel
10 = 24 Bits per Channel
11 = Reserved
R/W
CDCLKCON [12] Determine codec clock source
0 = Use internal codec clock source
1 = Get codec clock source from external codec chip
(For more information refer to Figure 10.3-2)
R/W
IMS [11:10] I2S master (internal/external) or slave mode select.
00 = Master mode (divide mode, using PCLK)
01 = Master mode (bypass mode, using I2SCLK)
10 = Slave mode (divide mode, using PCLK)
11 = Slave mode (bypass mode, using I2SCLK)
(For more information refer to Figure 10.3-2)
R/W
TXR [9:8] Transmit or receive mode select.
00 = Transmit only mode
01 = Receive only mode
10 = Transmit and receive simultaneous mode
11 = Reserved
R/W
LRP [7] Left/ Right channel clock polarity select.
0 = Low for left channel and high for right channel
1= High for left channel and low for right channel
R/W
SDF [6:5] Serial data format.
00 = I2S format
01 = MSB-justified (left-justified) format
10 = LSB-justified (right-justified) format
11 = Reserved
R/W
RFS [4:3] I2S root clock (codec clock) frequency select.
00 = 256 fs, where fs is sampling frequency
01 = 512 fs
10 = 384 fs
11 = 768 fs
R/W