Samsung S5PC100, User Manual

Page: 934 / 1863

MODEM INTERFACE S5PC100 USER’S MANUAL (REV1.0)
8.11-12
8.5 MSM INTERRUPT CLEAR REGISTER (MSMINTCLR, W, ADDRESS = 0XED50_8010)
MSMINTCLR Bit Description Reset Value
MSMINTCLR [31:0] Write access to this register with any data will clear the interrupt
pending register of MSM modem interface.
-
NOTE : The interrupt controllers of AP (S5PC100) receive level-triggered type interrupt requests. Therefore, interrupt requests
from MSM interface are maintained until the interrupt service routine clears the interrupt pending register by writing
any data into this register.
8.6 DMA REQUEST TX ADDRESS REGISTER USED AT DIRECT MODE (DMAREQ_TX_ADR, R/W,
ADDRESS = 0XED50_8014)
INT2AP Bit Description Reset Value
Reserved [31:30] Reserved 0
DMA_TX_ADR_1 [29:16] Modem interface requests the DMA to AP (DMA Controller) if
modem chip reads this address.
Source : DMA_MSM_Req[1]
0x17FE
Reserved [15:14] Reserved 0
DMA_TX_ADR_0 [13:0] Modem interface requests the DMA to AP (DMA Controller) if
modem chip reads this address.
Source : DMA_MSM_Req[0]
0x13FE
8.7 DMA REQUEST RX ADDRESS REGISTER USED AT DIRECT MODE (DMAREQ_RX_ADR, R/W,
ADDRESS = 0XED50_8018)
INT2AP Bit Description Reset Value
Reserved [31:30] Reserved 0
DMA_RX_ADR_1 [29:16] Modem interface requests the DMA to AP (DMA Controller) if
modem chip writes this address.
Source : DMA_MSM_Req[3]
0x1FFE
Reserved [15:14] Reserved 0
DMA_RX_ADR_0 [13:0] Modem interface requests the DMA to AP (DMA Controller) if
modem chip writes this address.
Source : DMA_MSM_Req[2]
0x1BFE