Samsung S5PC100, User Manual

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STATIC MEMORY CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.2-8
Field Bit Description Reset Value
AddrMode3 [13]
Select SMC ADDR Base for Memory Bank3
0 = SMC_ADDR is Half-word base address.
(SRAM_ADDR[20:0]
←
HADDR[21:1])
1 = SMC_ADDR is byte base address
(SMC_ADDR[20:0]
←
HADDR[20:0])
Note: If DataWidth0 is “0”, SMC_ADDR is byte base address.
(Ignored this bit.)
0
DataWidth3 [12]
Data bus width control for Memory Bank3
0 = 8-bit
1 = 16-bit
0
ByteEnable2 [11]
nWBE / nBE(for UB/LB) control for Memory Bank2
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
0
WaitEnable2 [10]
Wait enable control for Memory Bank2
0 = Disables WAIT
1 = Enables WAIT
0
AddrMode2 [9]
Select SMC ADDR Base for Memory Bank2
0 = SMC_ADDR is Half-word base address.
(SRAM_ADDR[20:0]
←
HADDR[21:1])
1 = SMC_ADDR is byte base address
(SMC_ADDR[20:0]
←
HADDR[20:0])
Note: If DataWidth0 is “0”, SMC_ADDR is byte base address.
(Ignored this bit.)
0
DataWidth2 [8]
Data bus width control for Memory Bank2
0 = 8-bit
1 = 16-bit
0
ByteEnable1 [7]
nWBE / nBE(for UB/LB) control for Memory Bank1
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
0
WaitEnable1 [6]
Wait enable control for Memory Bank1
0 = Disables WAIT
1 = Enables WAIT
0
AddrMode1 [5]
Select SMC ADDR Base for Memory Bank1
0 = SMC_ADDR is Half-word base address.
(SRAM_ADDR[20:0]
←
HADDR[21:1])
1 = SMC_ADDR is byte base address
(SMC_ADDR[20:0]
←
HADDR[20:0])
Note: If DataWidth0 is “0”, SMC_ADDR is byte base address.
(Ignored this bit.)
0
DataWidth1 [4]
Data bus width control for Memory Bank1
0 = 8-bit
1 = 16-bit
0