Samsung S5PC100, User Manual

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USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0)
8.10 -42
8.2.19 Device Periodic Transmit FIFO-n Size Register (DPTXFSIZn, R/W, Address = 0xED2 (n-
1)*04h)
FIFO_number: 1
≤
n
≤
15
This register holds the memory start address of each periodic TxFIFO to implement in Device mode. Each
periodic FIFO holds the data for one periodic IN endpoint. This register is repeated for each periodic FIFO
instantiated.
DPTXFSIZn Bit Description R/W Reset Value
DPTxFSize [31:16] Device Periodic TxFIFO Size
This value is in terms of 32-bit words
•
Minimum value is 4
•
Maximum value is 768
The power-on reset value of this register is the Largest
Device Mode Periodic Tx Data FIFO-n Depth. Write a new
value to this field.
R/W
n :1 (16'h300)
n :2 (16'h300)
n :3 (16'h300)
n :4 (16'h300)
n :5 (16'h300)
n :6 (16'h300)
n :7 (16'h300)
n :8 (16'h300)
n :9 (16'h300)
n :10 (16'h300)
n :11 (16'h300)
n :12 (16'h300)
n :13 (16'h300)
n :14 (16'h300)
n :15 (16'h300)
DPTxFStAddr [15:0] Device Periodic TxFIFO RAM Start Address
Holds the start address in the RAM for this periodic FIFO.
The power-on reset value of this register is sum of the
Largest Rx Data FIFO Depth, Largest Non-Periodic Tx Data
FIFO Depth, and all lower numbered Largest Device Mode
Periodic Tx Data FIFOn Depth specified.
If you have programmed new values for the RxFIFO, Non-
Periodic TxFIFO, or device Periodic TxFIFOs, write their
sum in this field. Programmed values must not exceed the
power-on value set.
R/W
n :1 (16'h1000)
n :2 (16'h3300)
n :3 (16'h3600)
n :4 (16'h3900)
n :5 (16'h3C00)
n :6 (16'h3F00)
n :7 (16'h4200)
n :8 (16'h4500)
n :9 (16'h4800)
n :10
(16'h4B00)
n :11
(16'h4E00)
n :12
(16'h5100)
n :13
(16'h5400)
n :14
(16'h5700)
n :15
(16'h5A00)