Samsung S5PC100, User Manual, Page: 607 / 1863

SYSTEM TIMER S5PC100 USER’S MANUAL (REV1.0)
7.2-10
7.2.4 TICK OBSERVATION REGISTER (TCNTO, R, Address = EA10_000C)
TCNTO Bit Description Reset Value
Tick Count Observation [31:0] Tick Count Observation Register 0x0
7.2.5 INTERRUPT COUNTER REGISTER (ICNTB, R/W, Address = EA10_0010)
Real Interrupt Counter Value = ICNTB+1.
If ICNTB value is 0, interrupt occurs at every TICK.
ICNTB Bit Description Reset Value
Interrupt Count Buffer
[31:0]
Interrupt Count Buffer Register
0x0
7.2.6 INTERRUPT OBSERVATION REGISTER (ICNTO, R, Address = EA10_0014)
ICNTO Bit Description Reset Value
Interrupt Count
Observation
[31:0] Interrupt Count Observation Register 0x0
7.2.7 INTERRUPT CONTROL AND STATUS REGISTER (INT_CSTAT, R/W, Address = EA10_0018)
INT_CSTAT Bit Description Reset Value
TCON Write Status [4]
TCON Write Status Interrupt Bit. After internal counters
are updated, this bit is asserted.
Clear by writing ‘1’ on this bit.
0x0
ICNTB Write Status
[3]
ICNTB Write Status Interrupt Bit. After internal counters
are updated, this bit is asserted.
Clear by writing ‘1’ on this bit.
0x0
TCNTB Write Status [2]
TCTNB Write Status Interrupt Bit. After internal counters
are updated, this bit is asserted.
Clear by writing ‘1’ on this bit.
0x0
INTCNT counter expired
Status
[1]
Interrupt counter expired (INTCNT=0) Interrupt Status
Bit. When timer interrupt is occurred, this bit is asserted.
Clear by writing ‘1’ on this bit.
Clear delay: 7 cycles of TCLK plus 2 cycles of PCLK
0x0
ICNTEIE
[0]
Interrupt counter expired (INTCNT=0) Interrupt Enables
1 = Enable
0 = Disable
0x0