Samsung S5PC100, User Manual, Page: 410 / 1863

S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER
5.1-27
4.2.8 PHY Control1 Register (PhyControl1, R/W, Address=0xE600_001C)
PHYCONTROL1 Bit Description R/W
Reset
Value
dqs_delay [31:28] Delay Cycles for DQS Cleaning R/W 0x0
Reserved [27:23] Should be zero 0x0
ctrl_offsetd [22:16]
This field is for debug purpose.
If this field is fixed, this should not be changed during
operation. This value is valid after ctrl_resync becomes HIGH
and LOW.
offset amount for 270' clock generation
ctrl_offsetd[6] = 1 : (tFS : fine step delay)
270' delay amount - ctrl_offsetd[5:0] x tFS
ctrl_offsetd[6] = 0 :
270' delay ctrl_offsetd[5:0] x tFS
R/W 0x0
drv_type [15]
Driving Type of Bidirectional Pins in Idle State
0x0 = Drive all to zeros,
0x1 = Pull down all
If CAS or read data latency is 2, this register must not set be to
0x0.
0x0
ctrl_offsetc [14:8]
Delay Offset for DQS Cleaning
Gate offset amount for DDR. If this field is fixed, this should not
be changed during operation. This value is valid after
ctrl_resync becomes HIGH and LOW.
ctrl_offsetc[6] = 1 : (tFS : fine step delay)
GATEout delay amount - ctrl_offsetc[5:0] x tFS
ctrl_offsetc[6] = 0 :
GATEout delay ctrl_offsetc[5:0] x tFS
R/W 0x0
ctrl_ref [7:4]
Reference Count for DLL Lock Confirmation
This field determines the period of time when ctrl_locked is
cleard.
0x0000 : Don’t use.
0x0001 : ctrl_flock is de-asserted during 6 clock cycles,
ctrl_locked is de-asserted.
0x0010 : ctrl_flock is de-asserted during 9 clock cycles,
ctrl_locked is de-asserted.
~
0x1111 : ctrl_flock is de-asserted during 48 clock cycles,
ctrl_locked is de-asserted.
R/W 0x4
fp_resync [3] Force DLL Resynchronization R/W 0x0