Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) 3D-ACCELERATOR
9.6-13
2 GLOBAL REGISTER
2.1 OVERVIEW
Global registers is a set of overall states in 3D-ACCELERATOR.
2.2 THE ROLE OF GB_PIPESTATE SFRS
Each bit field in GB_PIPESTATE represents whether the corresponding block processes the geometry data. If
one of bits is 1, then this means the geometry data is processed in the corresponding block. The 0 value
represents the corresponding block waits for the geometry data and does nothing. GB_PIPESTATE is used to
determine the timming when the state of each block is updated. For example, after CPU sending the geometry
data, CPU wants to set the next state of the per-fragment unit. If CPU updated the new state of the per-fragment
unit when the previsous geometry data is in the vertex shader, the remain data would be affected by the new state
of the per-fragment unit. The result would be wrong. In this case, CPU checks the GB_PIPESTATE and
determines where the gemoetry data is processed. CPU waits for the geometry data to be transferred after the
per-fragment unit. Only when all the blocks before the per-fragment unit is free, the state of the per-fragment unit
can be updated.
All the geometry data can be processed and sent to the frame buffer. At this moment, CPU can update the state
of the per-fragment unit safely. However, this can affect the performace of 3D-ACCELERATOR waiting the whole
pipeline to be empty. Regarding to the perfomance, this is not desirable. If CPU knows the proper time to update
states, then the perfomance will be increased. This is the reason why GB_PIPESTATE exists.
2.3 DATA TRANSFER USING 3D-ACCELERATOR’S INTERRTUP
The data transfer includes the modification of SFR values and the geometry data transfer; interrupts can be used
to change SFR values and send geometry data.
Interrupts from 3D-ACCELERATOR’s pipeline-state can be used to know when to change SFR values for a 3D-
ACCELERATOR block. SFR values for a block can be changed only when the previous blocks are empty for the
safe operation. Otherwise, the remained geometry data in the 3D-ACCELERATOR pipeline is affected by the new
SFR value instead of the previous SFR values intended to be applied to geometry data. CPU can repeat to read
the pipeline-state, which is known as polling, to know when to update SFRs. However, CPU should do another job
instead of investigating pipeline-state and spending cycles. In this case, CPU can set interrupt conditions and do
another job. If the interrupt condition is met and an interrupt occurs, CPU can change the SFR values.
Interrupts can be used to transfer geometry data. CPU transfers geometry data when there is free space in the
Host-FIFO of 3D-ACCELERATOR’s Host Interface. CPU can keep watching pipeline-state in order to know when
to transfer the other geometry data to the Host-FIFO of 3D-ACCELERATOR’s Host Interface with polling. This
wastes performance investigating the pipeline-state. Interrupts can be used for this situation. In this case, CPU
sets interrupt conditions for the next geometry data after sending a bunch of geometry data and performs another
pending job. When an interrupt occurs, CPU can transfer the rest of geometry data to 3D-ACCELERATOR.
Figure 9.6- 2 shows an example illustrating how to transfer geometry data.