Samsung S5PC100, User Manual, Page: 412 / 1863

S5PC100 USER’S MANUAL (REV1.0) DRAM CONTROLLER
5.1-29
tA: I/O output delay tB: Package bonding wire delay tC: Package board delay
tD: Board trace delay tE: I/O input delay
tDL: delay line delay
tAC: minimum CK-to-DQS timing of LPDDR/DDR2 memory spec. (LPDDR ( 1ns, DDR2 ( 0.5tCK)
tFS : Fine step delay in DLL, From PhyStatus0.ctrl_lock_value[9:0], tFS can beis calculated.
- If ctrl_half = 0, tFS = tCK / ctrl_lock_value[9:0].
- If ctrl_half = 1, tFS = tCK*0.5 / ctrl_lock_value[9:0]
ctrl_shiftc controls PVT-independent delay amount(tF) and ctrl_offsetc controls PVT-dependent delay
amount(tV).
Delay line programming value; tDL
≈
tAC + 2*(tB+tC+tD).
tDL = tF (ctrl_shiftc[2:0]) + tV (ctrl_offsetc[6:0])
If ctrl_shiftc[2:0] is 3'b100, tF is Tperiod/8
≈
0.9375ns. (If tCK is 7.5ns)
If ctrl_offsetc[6:0] is 7'b00010_00, tV is 0.320ns(40ps * 8) @ worst case (if tFS = 40ps)
Therefore tDL = tF + tV = 0. 0.320ns = 1.2575ns