Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) CRYPTO ENGINE BLOCK
11.3-23
4.3.12 FIFO-Tx Read Buffer (FTx_RdBuf, W, Address = 0xF411_0040~0xF411_0080)
FTx_RdBuf Bit Description Reset
Value
FTx_RdBuf
[31:0]
Read access to
FTx_RdBuf
makes FIFO-Tx to read data from the
FIFO memory regardless of the address given. That is, any
address between 0x0040 and 0x0080 triggers the FIFO memory
read. This feature lets the programmer use burst read from FIFO-
Tx
4.4 AES SPECIAL FUNCTION REGISTER (SFRS)
4.4.1 AES Control / Status Register (AES_Rx_CTRL, R/W, Address = 0xF404_0000)
AES_Rx_CTRL Bit Description Reset
Value
WrPrivMismatch [31]
SFR Write Access Privilege Mismatch Status bit. If set to ‘1’,
SFR Write Access Privilege Mismatch occurs.
Read only (Read Clear)
1’b0
RdPrivMismatch [30]
SFR Read Access Privilege Mismatch Status bit. If set to ‘1’,
SFR Read Access Privilege Mismatchoccurs.
Read only (Read Clear)
1’b0
Reserved [29:11] Reserved 19’h0
AesOutReady [10]
If set to ‘1’, AES Output Buffer is Full, and ARM or Rx FiFo is
permitted to Read current 128bits result data
Read only
1’b0
AesInReady [9]
If set to ‘1’, AES Input Buffer is Empty, and ARM or Rx FiFo is
permitted to write next 128bits data.
Read only
1’b1
AesContDecOn [8]
Continuous Decryption Enable Bits
0 = Decryption Key is changed
1 = Decryption Key is not changed
Read/Write
1’b0
CtrWidth [7:6]
Counter Mode Counter Width Bits
00 = 16Bits Counter
01 = 32Bits Counter
10 = 64Bits Counter
Read/Write
2’b00
AesOpMode [5:4]
AES Operation Mode Selection Bits
01 = ECB Mode
10 = CBC Mode
11 = CTR Mode
Read/Write
2’b0
AesOpDirection [3]
AES Operation Direction Selection Bit.
0 = Encryption
1’b0