Samsung S5PC100, User Manual, Page: 38 / 1863

BALL MAP & SIZE (SingleChip) S5PC100 USER’S MANUAL (REV1.0)
1.1-2
1.2 PIN NUMBER ORDER
Table 1.3-1 S5PC100 521 FCFBGA Pin Assignment
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Pin Number Order (1/4)
Ball Pin Name Ball Pin Name Ball Pin Name Ball Pin Name
A1 VSS B14 Xm1DATA[16] C27 Xm1DATA[4] G12 Xm1ADDR[12]
A2 VSS B15 Xm1ADDR[5] D1 Xm0ADDR[20] G13 Xm1ADDR[14]
A3 Xm0DATA[7] B16 Xm1ADDR[9] D2 Xm0BEn[0] G14 Xm1ADDR[0]
A4 Xm0DATA[10] B17 Xm1ADDR[7] D3 VSS G15 Xm1RASn
A5 Xm0DATA[2] B18 Xm1NSCLK D8 VDD_INT G16 Xm1ADDR[10]
A6 Xm0DATA[3] B19 Xm1WEn D9 Xm0REG G17 VDD_ARM
A7 Xm0DATA[8] B20 Xm1ADDR[3] D10 Xm1DATA[24] G18 VDD_ARM
A8 Xm0DATA[0] B21 Xm1DQM[1] D11 Xm1DATA[26] G19 VDD_ARM
A9 Xm0FRnB[1] B22 Xm1DATA[14] D12 Xm1DATA[25] G20 VDD_ARM
A10 Xm0IORDY B23 Xm1DATA[10] D13 Xm1DATA[22] G25 XpwmTOUT[0]
A11 Xm1DQS[3] B24 Xm1DATA[9] D14 Xm1DATA[19] G26 XuRXD[0]
A12 Xm1DQSn[3] B25 Xm1DQS[0] D15 VDD_INT G27 XuRXD[3]
A13 Xm1DATA[23] B26 Xm1DQSn[0] D16 VSS H1 Xm0ADDR[9]
A14 Xm1DQM[2] B27 VSS D17 Xm1CSn[1] H2 Xm0ADDR[5]
A15 Xm1DQS[2] C1 Xm0WEn D18 Xm1ADDR[15] H3 Xm0DATA[6]
A16 Xm1DQSn[2] C2 Xm0FALE D19 VSS H4 Xm0FRnB[0]
A17 Xm1ADDR[4] C3 Xm0DATA[14] D20 VDDQ_DDR H7 XefFSOURCE_0
A18 Xm1ADDR[13] C4 Xm0DATA[12] D25 Xm1DQM[0] H8 Xm0RESET
A19 Xm1ADDR[8] C5 Xm0DATA[11] D26 Xm1DATA[2] H9 Xm0CDn
A20 Xm1DATA[13] C6 Xm0DATA[15] D27 Xm1DATA[3] H10 Xm0BEn[1]
A21 Xm1DATA[12] C7 Xm0FRnB[2] E1 Xm0ADDR[0] H11 Xm1ADDR[11]
A22 Xm1DATA[15] C8 VSS E2 Xm0ADDR[11] H12 Xm1CKE[1]
A23 Xm1DQS[1] C9 Xm0IOWRn E3 VDDQ_M0 H13 Xm1CKE[0]
A24 Xm1DQSn[1] C10 Xm1DATA[31] E25 XpwmTOUT[1] H14 Xm1CASn
A25 Xm1DATA[7] C11 Xm1DATA[28] E26 Xm1DATA[1] H15 VDDQ_DDR
A26 VSS C12 Xm1DQM[3] E27 Xm1DATA[0] H16 VSS
A27 VSS C13 Xm1DATA[17] F1 Xm0ADDR[12] H17 VSS
B1 VSS C14 Xm1DATA[20] F2 Xm0ADDR[4] H18 VSS
B2 Xm0DATA[4] C15 Xm1DATA[18] F3 Xm0ADDR[18] H19 VSS
B3 Xm0DATA[9] C16 VDDQ_DDR F25 Xi2c0SCL H20 VSS
B4 Xm0DATA_RDn C17 Xm1SCLK F26 XuRTSn[0] H21 VDD_ARM
B5 Xm0DATA[13] C18 Xm1CSn[0] F27 XuRTSn[1] H24 XuTXD[0]
B6 Xm0DATA[1] C19 Xm1ADDR[1] G1 Xm0CSn[3] H25 XuRXD[2]
B7 Xm0FRnB[3] C20 Xm1DATA[11] G2 Xm0ADDR[13] H26 XuRXD[1]
B8 Xm0CSn[2] C21 VDDQ_DDR G3 Xm0ADDR[10] H27 XuTXD[2]
B9 VDDQ_M0 C22 VSS G7 XefVGATE_0 J1 Xm0DATA[5]
B10 Xm1DATA[30] C23 Xm1ADDR[2] G8 Xm0CFWEn J2 Xm0ADDR[1]
B11 Xm1DATA[29] C24 Xm1DATA[8] G9 Xm0CFOEn J3 Xm0ADDR[2]
B12 Xm1DATA[27] C25 Xm1DATA[6] G10 Xm0INPACKn J4 Xm0ADDR[16]
B13 Xm1DATA[21] C26 Xm1DATA[5] G11 Xm1ADDR[6] J7 Xm0INTRQ