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S5PC100 USER’S MANUAL (REV1.0)
I
2
C-BUS INTERFACE
8.2-11
3.1 MULTI-MASTER I
2
C-BUS CONTROL REGISTER
•
I2CCON0, R/W, Address = 0xEC10_0000
•
I2CCON1, R/W, Address = 0xEC20_0000
I2CCON
Bit
Description
Reset Value
Acknowledge generation
(1)
[7] I
2
C-bus acknowledge enable bit.
0 = Disables
1 = Enables
In Tx mode, the I2CSDA is free in the ACK time.
In Rx mode, the I2CSDA is L in the ACK time.
0
Tx clock source
selection
[6]
Source clock of I
2
C-bus transmit clock prescaler selection bit.
0 = I2CCLK = fPCLK /16
1= I2CCLK = fPCLK /512
0
Tx/Rx Interrupt (5)
[5]
I
2
C-Bus Tx/Rx interrupt enable/ disable bit.
0 = Disables, 1 = Enables
0
Interrupt pending flag
(2) (3)
[4] I
2
C-bus Tx/Rx interrupt pending flag. This bit cannot be written
to 1. If this bit is read as 1, the I2CSCL is tied to L and the I
2
C
is stopped. To resume the operation, clear this bit as 0.
0 = 1) No interrupt pending (If read).
2) Clear pending condition &
Resume the operation (If write).
1 = 1) Interrupt is pending (If read)
2) N/A (If write)
0
Transmit clock value (4)
[3:0] I
2
C-Bus transmit clock prescaler.
I
2
C-Bus transmit clock frequency is determined by this 4-bit
prescaler value, according to the following formula:
Tx clock = I2CCLK/(I2CCON[3:0]+1).
Undefined
NOTES:
1. Interfacing with EEPROM, the ACK generation may be disabled before reading the last data in order to generate the
STOP condition in Rx mode.
2. An
I
2
C-bus interrupt occurs 1)if a 1-byte transmits or receive operation is complete. in other word, ack period is finished.
2) If a general call or a slave address match occurs, or 3) if bus arbitration fails.
3. To adjust the setup time of SDA before SCL rising edge, I2CDS has to be written before clearing the I
2
C interrupt
pending bit.
4. I2CCLK is determined by I2CCON[6].
Tx clock can vary by SCL transition time.
If I2CCON[6]=0, I2CCON[3:0]=0x0 or 0x1 is not available.
5. If the I2CCON[5]=0, I2CCON[4] does not operate correctly.
Therefore, It is recommended that you should set I2CCON[5]=1, although you does not use the I
2
C interrupt.
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...