Samsung S5PC100, User Manual

Page: 1558 / 1863

HDMI S5PC100 USER’S MANUAL (REV1.0)
9.10-76
SPDIFIN_CONFIG_1 Bit Description Reset Value
U_V_C_P_report 2
Report for each subframe. Valid only if SPDIFIN_CONFIG.
data_align is set for 32-bit mode
0 = Neglects ‘user_bit’, ‘validity_bit’, ’channel status’
‘parity_bit’ of SPDIF format.
1 = Reports ‘user_bit’, ‘validity_bit’, ‘channel status’
‘parity_bit’ of SPDIF format
0
HDMI_burst_size 1
0 = 1 burst
1 = 2 burst
0
data_align 0
16-bit: Takes 16-bits from MSB in a subframe of SPDIF
format then concatenates two consecutive 16-bit data in one
32-bit register of SPDIFIN_DATA_BUF_x.
32-bit: Data from one subframe with zero padding to MSB
part. (ex: 0x00ffffff for 24-bit data) If stream mode, you
should set ‘word_length_value_mode’ as 1 and set
SPDIFIN_USER_VALUE.word_length_manual as 3’b000.
- These two modes is applied to both modes of
SPDIFIN_CONFIG.data_type, i.e. PCM or stream; see also
SPDIFIN_DATA_BUF_x.
0 = 16-bit mode
1 = 32-bit mode
0
3.136 SPDIFIN_CONFIG_2, R/W, ADDRESS = 0XF030_ 5014
SPDIFIN_CONFIG_2 Bit Description Reset Value
clk_divisor 3:0
SPDIFIN over-samples the SPDIF input signal with internally
made clock which is divided from system clock.
Recommended over-sampling ratio is 8~10, thus following
calculation holds.
Recommended SPDIFIN_internal_clock
= Sampling Frequency of SPDIF Input Signal * 64-bits * 10
times-over-sampling
(ex) 48 kHz * 64-bits * 10 times-over-sampling = 31 Mhz
SPDIFIN_internal_clock
= system_clock / (clk_d 1)
(SPDIFIN_internal_clock
≤
135 Mhz)
0000