Samsung S5PC100, User Manual

Page: 459 / 1863

ONENAND CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.3-22
4.23 INTERRUPT PIN ENABLE REGISTER (INT_PIN_ENABLE, R/W, ADDRESS = 0XE710_01A0)
INT_PIN_ENABLE Bit Description Reset Value
Reserved [31:1] Reserved
INT [0]
Interrupt Pin Enable. Enables interrupt information to be
transmitted to the host. An interrupt is only sent to the host if a
bit is set in the int_error_status register, the corresponding bit
is set in the INT_ERR_MASK register AND this bit is set.
0 = Does not report interrupts
1 = Send interrupt information to the host.
0
4.24 INTERRUPT MONITOR CYCLE COUNT REGISTER (INT_MON_CYC, R/W, ADDRESS = 0XE710_01B0)
INT_MON_CYC Bit Description Reset Value
Reserved [31:12] Reserved
Int_Mon_Cyc_ Cnt [11:0]
Sets the number of cycles in between checks of the
int_error_status register and the memory device’s status
register. This register is used if the Flash configuration register
bit IOBE is clear.
0x01F4
4.25 ACCESS CLOCK REGISTER (ACC_CLOCK, R/W, ADDRESS = 0XE710_01C0)
ACC_CLOCK Bit Description Reset Value
Reserved [31:3] Reserved
Access_Clocks [2:0]
Sets the number of cycles required to cover the access time of
the Flash memory device.
Follows the formula (35ns / ClkPeriod ) + 1
2X Clock Flash Clock Access_Clocks
166MHz 83MHz 3
134 67 3
100 50 2
60 30 2
0x3
4.26 ERROR BLOCK ADDRESS REGISTER (ERR_BLK_ADDR, R, ADDRESS = 0XE710_01E0)
ERR_PAGE_ADDR_1 Bit Description Reset Value
Reserved [31:12] Reserved
FBA_Fail [11:0]
After a program, load or erase error interrupt, this register
holds the block address of the failing operation. Read-Only.
0