USB HOST CONTROLLER
S5PC100 USER’S MANUAL (REV1.0)
8.9-38
UHCRHPSTAT
1
Bit
Description
R/W
Reset Value
reporting is not supported, this bit is forced to 0. If this
bit is cleared, all power operations are normal for this
port. If set, an over-current condition exists on this port.
This bit always reflects the over-current input signal.
The HCD writes a 1 to this bit to initiate a resume.
Writing a 0 has no
effect. A resume is initiated only if PortSuspendStatus is
set.
0 = No over-current condition.
1 = Over-current condition detected.
PSS [2]
(read)
PortSuspendStatus / (write) SetPortSuspend
This bit indicates if the port is suspended or in the
resume sequence (1). If it is a 0, the port is not
suspended or in the resume sequence. It is set by a set
suspend state write and cleared if PortSuspendStatus
change is set at the end of the resume interval. This bit
cannot be set if CurrentConnectStatus is cleared. This
bit is also cleared if PortResetStatus change is set at
the end of the port reset, or if the UHC is placed in the
USBRESUME state. If an upstream resume is in
progress, it must propagate to the HC. The HCD sets
the PortSuspendStatus bit by writing a 1 to this bit.
Writing a 0 has no effect. If CurrentConnectStatus is
cleared, this write does not set PortSuspendStatus;
instead it sets ConnectStatusChange. This informs the
driver that it attempted to suspend a disconnected port.
0 = Port is not suspended.
1 = Port is suspended.
R/W
PES
[1]
(read) PortEnableStatus / (write) SetPortEnable
This bit indicates whether the port is enabled (1) or
disabled (0). The root hub clears this bit if an over-
current condition, disconnect event, switched-off power,
or operational bus error, such as babble, is detected.
This change also causes the port enabled status
change bit (UHCRHPS1/2/3[PESC] to be set. The HCD
sets the PortEnableStatus bit, by writing a 1
to it, and clears this bit by writing a 1 to clear port
enable (UHCRHPS1/2/3[CCS], bit 0 of this register). If
CurrentConnectStatus is cleared, this write does not set
PortEnableStatus, but instead sets
ConnectStatusChange. This informs the driver that it
attempted to enable a disconnected port. Writing a 0 to
the PortEnableStatus bit has no effect. This bit is also
set, if
not already, at the completion of a port reset when reset
status change (UHCRHPS1/2/3[PRSC]) is set or port
suspend if suspend status change
(UHCRHPS1/2/3[PSSC]) is set
R/W
Summary of Contents for S5PC100
Page 21: ...MEMORY MAP S5PC100 USER S MANUAL REV1 0 1 2 2 ...
Page 34: ...S5PC100 USER S MANUAL REV1 0 BALL MAP SIZE POP 1 1 9 1 4 MCP CONNECTION ...
Page 49: ...IROM CODE S5PC100 USER S MANUAL REV1 0 2 6 4 12 Mhz 300 0 Mhz 100 0 Mhz 79 5 Mhz 20 6 Mhz ...
Page 174: ...CLOCK CONTROLLER S5PC100 USER S MANUAL REV1 0 2 3 24 Rs 0ohm Rf 1Mohm CL 10 35pF ...
Page 322: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 4 Figure 3 2 2 S5PC100 Coresight Structure ...
Page 330: ...CORESIGHT S5PC100 USER S MANUAL REV1 0 3 2 12 Figure 3 2 7 ETB Block Diagram ...
Page 345: ...S5PC100 USER S MANUAL REV1 0 ASYNC BRIDGE 3 4 3 Figure 3 4 2 Asynchronous Bridge Components ...
Page 359: ...S5PC100 USER S MANUAL REV1 0 VECTORED INTERRUPT CONTROLLER 4 1 3 Figure 4 1 2 VIC Daisy Chain ...
Page 651: ...S5PC100 USER S MANUAL REV1 0 UART 8 1 27 Figure 8 1 10 UINTSP UINTP and UINTM block diagram ...
Page 652: ...UART S5PC100 USER S MANUAL REV1 0 8 1 28 NOTES ...
Page 743: ...S5PC100 USER S MANUAL REV1 0 MIPI HSI INTERFACE CONTROLLER 8 6 13 ...
Page 756: ...MIPI HSI INTERFACE CONTROLLER S5PC100 USER S MANUAL REV1 0 8 6 26 NOTES ...
Page 800: ...MIPI CSIS S5PC100 USER S MANUAL REV1 0 8 8 10 NOTES ...
Page 816: ...USB HOST CONTROLLER S5PC100 USER S MANUAL REV1 0 8 9 16 ...
Page 935: ...S5PC100 USER S MANUAL REV1 0 MODEM INTERFACE 8 11 13 NOTES ...
Page 1111: ...S5PC100 USER S MANUAL REV1 0 IMAGE ROTATOR 9 2 3 3 4 180 DEGREE ROTATION ...
Page 1112: ...IMAGE ROTATOR S5PC100 USER S MANUAL REV1 0 9 2 4 3 5 90 AND 270 DEGREE ROTATION ...
Page 1118: ...S5PC100 USER S MANUAL REV1 0 CAMERA INTERFACE 9 3 3 Figure 9 3 2 Camera Interface Overview ...
Page 1181: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 6 Figure 9 4 5 YCbCr4 2 2 Color Format ...
Page 1199: ...JPEG S5PC100 USER S MANUAL REV1 0 9 4 24 NOTES ...
Page 1245: ...3D ACCELERATOR S5PC100 USER S MANUAL REV1 0 9 6 18 ...
Page 1353: ...TVOUT VIDEO DAC S5PC100 USER S MANUAL REV1 0 9 7 32 ...
Page 1452: ...S5PC100 USER S MANUAL REV1 0 VIDEO PROCESSOR 9 8 43 NOTES ...
Page 1482: ...MIXER S5PC100 USER S MANUAL REV1 0 9 9 30 NOTES ...
Page 1664: ...S5PC100 USER S MANUAL REV1 0 I2S CONTROLLER 5 1CH 10 2 31 NOTES ...
Page 1701: ...AC97 CONTROLLER S5PC100 USER S MANUAL REV1 0 10 4 18 NOTES ...
Page 1731: ...SPDIF TRANSMITTER S5PC100 USER S MANUAL REV1 0 10 6 16 NOTES ...
Page 1744: ...S5PC100 USER S MANUAL REV1 0 ADC AND TOUCH SCREEN INTERFACE 10 7 13 NOTES ...
Page 1750: ...KEYPAD INTERFACE S5PC100 USER S MANUAL REV1 0 10 8 6 Figure 10 8 7 Keypad I F Block Diagram ...
Page 1755: ...S5PC100 USER S MANUAL REV1 0 KEYPAD INTERFACE 10 8 11 NOTES ...
Page 1779: ...SECURE DOMAIN MANAGER S5PC100 USER S MANUAL REV1 0 11 2 22 NOTES ...