Samsung S5PC100, User Manual, Page: 1255 / 1863

3D-ACCELERATOR S5PC100 USER’S MANUAL (REV1.0)
9.6-28
If the size of the geometry is not a multiples of 4, then send addtitional DWORD (usually 0x00000000) into the
Vertex Buffer. The additional DWORDs for dword-aligned does not affect the value of HI_ATTRIB
n _VBCT-
RL.Range. The value of actual index range must be written in HI_ATTRIB n _VBCTRL.Range.
Note that NaN or infinite floating point or half-float value must not be written in the Vertex Buffer just like
Non-Index Mode
.
Also, note that the geometry data in the Vertex Buffer must be DWORD aligned . Refer to the “Attribute
Control Register” in section “HOST INTERFACE SPECIAL REGISTERS.”
3.7 HOW TO USE THE VERTEX BUFFER AS A TEMPORAL BUFFER USING INTERRUPTS
There are 32 DWORD space in Host-FIFO. If CPU sends a lot of DWORDs with HI_DWSPACE polling, CPU has
to waste lots of cycles reading HI_DWSPACE without doing any other useful job until all the DWORDs are
transferred. This is an undesirable situation.
Vertex buffer and interrupt scheme can be used in this situation. Vertex buffer is used for one-time used
geometries in this situation: remind that Vertex Buffer usually stores geometry data which is supposed to be used
several times for performance.
CPU sends a part of DWORDs for geometries into Vertex Buffer instead of Host-FIFO. After saving DWORDs into
Vertex Buffer, CPU sets 3D-ACCELERATOR’s interrupt scheme making the interrupt-unit send an interrupt to
CPU when the values of GB_PIPESTATE for Host-FIFO and Host Interface become zero. At this time, CPU can
do other valuable job, such as Operating-System or Sound related processes, waiting for an interrupt from 3D-
ACCELERATOR. If an interrupt from 3D-ACCELERATOR is occurred and CPU is allowed to handle the
geometry-sending process, CPU continues to send the rest of geometries using the same procedure.
You can make an interrupt occur when all the 3D-ACCELERATOR pipeline stages become empty. You can make
your own decision when to make an interrupt occur. There is one thing you should pay attention to in this case:
you must send the exact number of vertices. For example, when the Primitive-Engine, which is the next block to
the Vertex Cache, is supposed to get a TRIANGLE data, the number of vertices must be the multiples of 3. If
(3n+1) vertices are sent and interrupt unit is waiting for the HI_PIPESTATE to be zero, an interrupt from 3D-
ACCELERATOR never occurs under this situation because the Primitive-Engine’s value of HI_PIPESTATE is 1
waiting for another two vertices. (However, if the Primitive-Engine is set to receive triangle strip data, the number
of transferred vertices is not important.)
If Vertex Buffer is used in this way, Vertex Cache is suggested to be disabled because all DWORDs (or
Indices) are used only one time; Vertex Cache does not have Hit-Case
.