Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) ONENAND CONTROLLER
5.3-1
5.3
ONENAND CONTROLLER
1 OVERVIEW
S5PC100 supports external 16-bit bus for both asynchronous and synchronous OneNAND external memory via
shared memory port 0. The controller is a complete embedded controller that interfaces directly to Input/ Output
(I/O) drivers in the I/O pad ring that connect to OneNAND Flash memory devices.
1.1 FEATURE
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Supports maximum 2 chip selects that should be same type device.
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Supports asynchronous / synchronous muxed OneNAND memory
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Supports 16-bit wide external memory data paths
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Supports Data Buffering: Required to achieve maximum performance
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Asynchronous FIFOs between the controller and the system interface for speed matching
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Read and write protocols implemented with bus interface read and write commands.
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Erase commands implemented through address mapping.
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Programmable-sized burst transfers.
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Support for multiple memory devices in the OneNAND family with a single bus interface protocol.
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Supported transfer types are INCRx transactions of one word and SINGLE word transactions for the register
slave. Transfers of a size less than width are not supported.
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Supports 4-way and 2-way interleaving operation for Program and Read operations
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Provision for software reset in which the controller is reset, but register values are retained
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Supports write-synchronous mode if OneNAND device ID is 0x0040, 0x0058, 0x0050, 0x0068, 0x0060, and
0x0078