Samsung S5PC100, User Manual, Page: 189 / 1863

S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER
2.3-39
10.4 CLOCK OUTPUT CONFIGURATION REGISTER
Internal clocks can be monitored through XCLKOUT PAD. CLK_OUT register selects an internal clock from PLL
outputs, ARMCLK, HCLKD0, HCLKD1, PCLKD0, PCLKD1, 30MHz, 48MHz, 27MHz, 54MHz, RTC, and TICK. It
also divides the selected clock. This is just for debugging. Do not supply this to other components as clock.
10.4.1 Select Clock Output (CLK_OUT, R/W, Address = 0xE010_0400)
CLK_OUT Bit Description Reset Value
Reserved [31:24] Reserved 0x000
DIVVAL [23:20] Divide ratio (Divide ratio = 1) 0x0
Reserved [19:17] Reserved 0x000
00000 = FOUT
APLL
/4 0x0
00001 = FOUT
MPLL
00010 = FOUT
EPLL
00011 = FOUT
HPLL
00100 = HCLKD1
00101 = HCLKD0
00110 = PCLKD1
00111 = PCLKD0
01000 = HCLKD2
01001 = ARMCLK/4
01010 = RTC clock from PAD
01011 = RTC tick
01100 = CLK48M
01101 = CLK27M
01110 = CLK30M
01111 = VCLK_54
CLKSEL [16:12]
10000 = DOUT
DCLKCMP [11:8]
This field changes the clock duty of DCLK. Thus, it must be
smaller than DCLKDIV. It is valid only if CLKSEL is 5’b10000.
0x0
If the DCLKDIV is n, low level duration is (n+1).
High level duration is ((D 1) – (n+1))
DCLKDIV [7:4] DCLK divide value 0x0
DCLK frequency = source clock / (D 1)
Reserved [3:2] Reserved 0x0
DCLKSEL [1] Select DCLK source clock (0: PCLK, 1: 48MHz) 0
DCLKEN [0] Enable DCLK (0:Disables, 1:Enables) 0
Clocks in CLKSEL can be referred at Figure 2.3-3.