Samsung S5PC100, User Manual

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Power Management S5PC100 USER’S MANUAL (REV1.0)
2.4-12
Figure 2.4-1 EPLL operation diagram).
After wakeup from DEEP-IDLE / DEEP-STOP mode, P/M/S setting to EPLL_CON(@0xE010_0108) should be
done, and EPLL_EN should be enabled by setting ENABLE[31] to 1’b1 in that register. After these setting is done,
EPLL_RET should be released by setting EPLL_RET_RELEASE[30] to 1’b1 in OTHERS register.
Reset by PRESETn
EPLL is enabled by system initialization
By setting EPLL _RET_ RELEASE[30]
in OTHERS register
Reset by PRESETn
DEEP _ IDLE _ MODE
SFR _ PWR _ CFG[ 30 ]
( TOP _ LOGIC _ ON _ DIDLE )
EPLL _ EN
EPLL _ RET
EPLL _ DOWN
EPLL _ CLK
DEEP _ STOP _ MODE
SFR _ STOP _ CFG [8]
( TOP _ LOGIC _ ON _ STOP )
0
0
Figure 2.4-1 EPLL Operation Diagram
3.5 STOP MODE
In STOP mode, clock to modules except RTC, and ALIVE module, is disabled, PLLs are disabled, and
unnecessary oscillators are selectively disabled so that dynamic power consumption is minimized. In this mode,
Cortex-A8 Core enters into Standby mode. Therefore, current application program that was running in NORMAL
mode, stops in STOP mode and waits for wakeup event to resume.
To enter STOP mode:
1. Set CFG_STANDBYWFI field of PWR_CFG to 2'b10.
2. Set PMU_INT_DISABLE bit of OTHERS register to 1’b1 to prevent interrupts from occurring while entering
STOP mode.
3. Execute Wait For Interrupt instruction (WFI).
PMU performs the following sequence to enter STOP mode.
1. Completes all active bus transactions.
2. Completes all active memory controller transactions.
3. Initiates external DRAM to enter self-refresh mode (to preserve DRAM contents).
4. Mask input clock using internal signal in PMU.
5. Disables all PLLs.
6. Selectively disables OSCs except 32.768kHz.