Samsung S5PC100, User Manual

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DISPLAY CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
9.1-48
VIDCON0 Bit Description Reset Value
1 = Start of a frame (only once per frame)
Reserved [15:14] Reserved
CLKVAL_F [13:6] Determines the rates of VCLK and CLKVAL[7:0]
VCLK = HCLK / (1) where CLKVAL >= 1
Note. 1. The maximum frequency of VCLK is 66MHz.
2. CLKSEL_F register selects Video Clock Source
0
VCLKFREE [5] VCLK Free run control ( Only valid at the RGB IF mode)
0 = Normal mode ( control by ENVID)
1 = Free-run mode
0
CLKDIR [4] Selects the clock source as direct or divide using CLKVAL_F
register
0 = Direct clock (frequency of VCLK = frequency of Clock
source)
1 = Divided by CLKVAL_F
0x00
Reserved [3] Should be 0 0x0
CLKSEL_F [2] Selects the Video Clock source
0 = HCLK
1 = SCLK_LCD
0
ENVID [1] Video output and the logic immediately enable/ disable.
0 = Disables the video output and the Display control signal.
1 = Enables the video output and the Display control signal. 0
ENVID_F [0] Video output and the logic enable/disable at current frame end.
0 = Disables the video output and the Display control signal.
1 = Enables the video output and the Display control signal.
* If this bit is set on and off, then you will read “H” and video
controller enable until the end of current frame.
0
NOTE: Display On: ENVID & ENVID_F set to “1”
Direct Off: ENVID & ENVID_F set to “0” simultaneously
Per Frame Off: ENVID_F set “0” & ENVID set”1”
Caution 1 : If the VIDCON0 is setting for Per Frame off in interlace mode, the value of INTERLACE_F should be
set to “0” in the same time.
Caution 2 : If display controller is off using direct off, it is impossible to turn on the display controller without reset.