Samsung S5PC100, User Manual

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SPDIF TRANSMITTER S5PC100 USER’S MANUAL (REV1.0)
10.6-10
6.2 DETAILED DESCRIPTION
6.2.1 Clock Control Register (SPDCLKCON, R/W, Address = 0XF260_0000)
SPDCLKCON Bit Description Reset Value
Reserved [31:3] Reserved 0
Main Audio Clock
Selection
[2]
0 = Internal clock (SCLK_SPDIF)
1 = External clock (I_MCLK_EXT)
0
SPDIFOUT clock down
ready
(read only)
[1] 0 = Clock-down not ready
1 = Clock-down ready 1
SPDIFOUT power on [0] 0 = Power Off 1 = Power On 0
6.2.2 SPDIFOUT Control Register (SPDCON, R/W, Address = 0XF260_0004)
SPDCON Bit Description Reset Value
Reserved [31:26] Reserved 0
FIFO Level [25:22]
FIFO Level Monitoring (Read Only)
FIFO depth is 8
*0: Empty of FIFO Level, 8: Full of FIFO Level
0000
FIFO Level Threshold [21:19]
FIFO Threshold Level is controllable
000 = 0-FIFO Level
001 = 1-FIFO Level
010 = 2-FIFO Level
011 = 3-FIFO Level
100 = 4-FIFO Level
101 = 5-FIFO Level
110 = 6-FIFO Level
111 = 7-FIFO Level
000
FIFO transfer mode [18:17]
00 = DMA transfer mode
01 = Polling mode
10 = Interrupt mode
11 = Reserved
00
FIFO_level Interrupt
Status
[16]
Read Operation
0 = No interrupt pending.
1 = Interrupt pending.
Write Operation
0 = No effect.
1 = Clear this flag.
0
FIFO_level Interrupt
Enable
[15]
0 = Interrupt masked
1 = Interrupt enable
0