Samsung S5PC100, User Manual

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S5PC100 USER’S MANUAL (REV1.0) STATIC MEMORY CONTROLLER
5.2-7
4.1 SMC BUS WIDTH & WAIT CONTRL REGISTER (SMC_BW, RW, ADDRESS=0XE700_0000)
Field Bit Description Reset Value
Reserved [31:24] Reserved 0
ByteEnable5 [23]
nWBE / nBE(for UB/LB) control for Memory Bank5
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
0
WaitEnable5 [22]
Enables Wait for Memory Bank5
0 = Disables WAIT
1 = Enables WAIT
0
AddrMode5 [21]
Select SMC ADDR Base for Memory Bank5
0 = SMC_ADDR is Half-word base address.
(SRAM_ADDR[20:0]
←
HADDR[21:1])
1 = SMC_ADDR is byte base address
(SMC_ADDR[20:0]
←
HADDR[20:0])
Note: If DataWidth0 is “0”, SMC_ADDR is byte base address.
(Ignored this bit.)
0
DataWidth5 [20]
Data bus width control for Memory Bank5
0 = 8-bit
1 = 16-bit
0
ByteEnable4 [19]
nWBE / nBE(for UB/LB) control for Memory Bank4
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
0
WaitEnable4 [18]
Enables Wait for Memory Bank4
0 = Disables WAIT
1 = Enables WAIT
0
AddrMode4 [17]
Select SMC ADDR Base for Memory Bank4
0 = SMC_ADDR is Half-word base address.
(SRAM_ADDR[20:0]
←
HADDR[21:1])
1 = SMC_ADDR is byte base address
(SMC_ADDR[20:0]
←
HADDR[20:0])
Note: If DataWidth0 is “0”, SMC_ADDR is byte base address.
(Ignored this bit.)
0
DataWidth4 [16]
Data bus width control for Memory Bank4
0 = 8-bit
1 = 16-bit
0
ByteEnable3 [15]
nWBE / nBE(for UB/LB) control for Memory Bank3
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
0
WaitEnable3 [14]
Wait enable control for Memory Bank3
0 = Disables WAIT
1 = Enables WAIT
0