Samsung S5PC100, User Manual

Page: 1642 / 1863

S5PC100 USER’S MANUAL (REV1.0) I2S CONTROLLER(5.1CH)
10.2-9
6.4 EXAMPLE CODE
TX CHANNEL
The I2S TX channel provides a single stereo compliant output. The transmit channel operates in master or
slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA
access.
The processor must write words in multiples of two (i.e. for left and right audio sample). The words are serially
shifted out timed with respect to the audio bitclk, BCLK and word select clock, LRCLK.
TX Channel has 64X32 bits wide FIFO where the processor or DMA writes up to 16 left/ right data samples
after enabling the channel for transmission.
For Example:
Ensure the PCLK and CODCLKI are coming correctly to the I2S controller and FLUSH the TX FIFO using the
TFLUSH bit in the I2SFIC Register (I2S FIFO Control Register).
Please ensure that I2S Controller is configured in one of the following modes.
•
TX only mode
•
TX/RX simultaneous mode
This is done by programming the TXR bit in the I2SMOD Register (I2S Mode Register).
1. Then Program the following parameters according to the need
♦
IMS
♦
SDF
♦
BFS
♦
BLC
♦
LRP
For Programming, the above-mentioned fields please refer to I2SMOD Register (I2S Mode Register).
2. After ensuring that the input clocks for I2S controller are up and running and step 1 and 2 have been
completed, you can write to TX FIFO.
The write to the TX FIFO has to be carried out thorough the I2STXD Register (I2S TX FIFO Register).
This 32-bit data occupies position 0 of the FIFO and any further data is written to position 2, 3 and so on.